Closed
Milestone
Bug fixing
The aim of this milestone is to do bug-fixing of known defects in the IP Core
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
33
- Unify "others" clause!
- RX Buffer commands filtration
- Reference test problem
- Add sync. chain attributes.
- ipyxact_parser is checked in as a submodule, but not declared in .gitmodules
- Fix ALC
- interrupt RXBNEI is set, but the RX FIFO is empty
- Buffer Data endianess
- Endian fix
- interrupt enable/mask/status
- TXT Buffer in bus-off
- Bus off time
- Software reset via MODE[RST] should reset the whole core
- Interrupt enable, mask bug-fix
- Sanity test failing
- fix byte enable
- Remove obsolete config options
- Hard sync in the EDL
- Transceiver delay
- Add TXT Buffer protection
- Fix the DLC reception
- Event logger BRS bugfix
- RX Buffer timestamp bug
- test: frame generation: inconsistent position of CAN ID in base frames
- VHDL feedback replacement with proper clock enable on flip flops
- Synthesis warning research
- 64 bit timestamp alignemt
- Bit rate shifting
- Code formatting
- Change the license header
- TODO research
- Rename the registers entity
- Bug-fix of the switching between data rates