Status Job Pipeline Stage Name Duration Coverage
passed #103465
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar deploy pages

00:01:06

passed #103464
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar coverage process_coverage

00:01:36

94.3%
failed #103463
master
e17305b2
allowed to fail
#37105 by Ille, Ondrej, Ing.'s avatar test_gates test_gates_compliance

00:36:37

failed #103462
master
e17305b2
allowed to fail
#37105 by Ille, Ondrej, Ing.'s avatar test_gates test_gates_simple

02:00:00

failed #103461
master
e17305b2
allowed to fail
#37105 by Ille, Ondrej, Ing.'s avatar test_rtl test_compliance_full_max

00:28:04

failed #103460
master
e17305b2
allowed to fail
#37105 by Ille, Ondrej, Ing.'s avatar test_rtl test_compliance_full_typ

01:06:20

failed #103459
master
e17305b2
allowed to fail
#37105 by Ille, Ondrej, Ing.'s avatar test_rtl test_compliance_short

00:11:44

passed #103458
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar test_rtl test_nightly

01:02:57

passed #103457
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar test_rtl test_fast_fpga

00:19:02

passed #103456
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar test_rtl test_fast_asic

00:14:18

passed #103455
master
e17305b2
vps
#37105 by Ille, Ondrej, Ing.'s avatar build run_synthesis

00:12:08

passed #103454
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar build build_linux_driver

00:00:25

passed #103453
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar build build_doc

00:02:00

passed #103452
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar build build_driver

00:01:36

passed #103451
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar build build_ip_and_tests

00:06:17

passed #103450
master
e17305b2
#37105 by Ille, Ondrej, Ing.'s avatar precheck check_component

00:00:14

passed #103328
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar deploy pages

00:01:04

passed #103327
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar coverage process_coverage

00:01:43

94.3%
failed #103326
master
e17305b2
allowed to fail
#37075 by Ille, Ondrej, Ing.'s avatar test_gates test_gates_compliance

00:35:03

failed #103325
master
e17305b2
allowed to fail
#37075 by Ille, Ondrej, Ing.'s avatar test_gates test_gates_simple

02:00:00

failed #103324
master
e17305b2
allowed to fail
#37075 by Ille, Ondrej, Ing.'s avatar test_rtl test_compliance_full_max

00:28:02

failed #103323
master
e17305b2
allowed to fail
#37075 by Ille, Ondrej, Ing.'s avatar test_rtl test_compliance_full_typ

01:08:10

failed #103322
master
e17305b2
allowed to fail
#37075 by Ille, Ondrej, Ing.'s avatar test_rtl test_compliance_short

00:11:12

failed #103321
master
e17305b2
allowed to fail
#37075 by Ille, Ondrej, Ing.'s avatar test_rtl test_nightly

01:04:09

passed #103320
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar test_rtl test_fast_fpga

00:19:09

passed #103319
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar test_rtl test_fast_asic

00:14:10

passed #103318
master
e17305b2
vps
#37075 by Ille, Ondrej, Ing.'s avatar build run_synthesis

00:12:07

passed #103317
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar build build_linux_driver

00:00:23

passed #103316
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar build build_doc

00:02:32

passed #103315
master
e17305b2
#37075 by Ille, Ondrej, Ing.'s avatar build build_driver

00:01:38