VHDL feedback replacement with proper clock enable on flip flops
According to Xilinx and Altera design guidlines for VHDL language automatic inferrence of clock enable signal is used in clocked process when following access type is done:
sample_proc:process(clk, res_n) begin if res_n = '0' then register <= reset_value; elsif rising_edge(clk) then if register_sel = '1' then register <= value; end if; end if; end process;
This allows to write access to the registers without assigning the value to the register in the else branch. In the CAN FD IP core all the registers are driven by themselves directly after the "elsif rising_edge(clk) then" statement. Assignment of different value is performed lower in the process code causing following behaviour: assign its old value or new value if any logic is active.
This explicit assignment in each clock cycle causes synthesis of feedback paths from the current register state (verified in RTL viewer of Quartus) and inferrence of additional multiplexer between the old value and new value. The design size can be significantly reduced if the assignments of the old values would be removed. This is especially the case in Protocol control, Prescaler, and Can_fd_registers!
The aim of this task is to group all the assignments of the default value directly after the rising_edge(clk_sys), group them together, and implement a simple way how to not use these assignments (generic or pragma...). Perform the sanity test simulation and verify its functionality! Next perform synthesis and check the resource usage and inference of the clock enable signal on those flip-flops!
Check the synthesis size with and without this option!