Explore projects

CAN with Flexible Data-rate IP Core developed at Department of Measurement of FEE CTU. See the list of related CAN projects and IP core integrations.

RISC-V processor designed in VHDL to match QtRvSim

pap-rvapo, but with C instead of Rust, and minor changes to cpu design

Web pages of OSY, see http://osy.pages.fel.cvut.cz/.

Zadání domácích úkolů pro předmět Modelování a simulace dynamických systémů.

Firmware kostky Open-Cube (https://maglab.fel.cvut.cz/open-cube/)

Sample project which verifies correct system setup. If the project can be built and started, the system has the correct setup.