Hard sync in the EDL
According to CAN FD specification Hard synchronisation should be performed in the EDL bit of CAN FD Frame. In the actual implementation this Hard synchronisation is omitted since Prescaler did not support Hard synchronisation in the middle of CAN Frame. In extreme cases (e.g. setting nominal SJW to 0) this could cause improper operation and inability to receive CAN FD frames.
The aim of this task is to add Hard-synchronisation in the EDL bit of CAN FD Frame.