Implement feature test for secondary sampling point user defined offset.
All options of SW offset, measured offset, SW + measured offset must be executed.
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Hi,
I added 3 sample signals to Status Bus in:
#260 (closed)
These are:
Sample trigger for Nominal Bit Time delayed by 1 clock cycle.
Sample trigger for Data Bit Time delayed by 1 clock cycle.
Sample trigger for Secondary Sample delayed by 1 clock cycle.
Little Design description:
If Core is transmitter, it is using Nominal Sampling point up to Bit-rate switch in EDL(FDF) bit.
After the switch, it will start using Data-Sample. Secondary sample point is invisible to
CAN Core (it is used only in Bus sampling module. CAN Core is still processing receive data
with Data Sample. To make sure that correct data are processed (since RX data might not be
yet there due to roundtrip), data into bit-destuffing are driven from post bit stuffing data.
This-way, Protocol Control receives what it transmitted in the Same bit. Note that this does
not mind since after bit-rate switch Core is the only transmitter.
Now to the error handling. If the Core which is transmitting in Data-Bit rate is automatically
receiving what it transmitted, then it has no way of knowing what has happened on the bus
(what errors are there). But what types of Errors does transmitter in Data-Phase needs
to detect? It will detect Bit-errors in Bus Sampling via secondary sample point. It should detect,
Stuff errors if some other unit starts transmitting Error Frame. But if this happends, the unit
will anyway detect Bit-Error sooner or later (due to stuff bit).
To sum it up: Transmitter in Data phase needs to only detect bit errors and it will even recognize
error frame by bit error detection mechanism.
Now to the test:
I would propose to wait for a Bit-rate switch (sp_control signal is also available in Status Bus),
and then measure number of clock cycles it takes for first occurence of Secondary Sample Point.