Commit 08960454 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '205-ssp-offset-feature-test' into 'master'

doc: Fix datasheet link

Closes #205

See merge request !311
parents 72ab7315 4b68c064
Pipeline #14494 failed with stages
in 76 minutes and 46 seconds
......@@ -22,7 +22,7 @@ Architecture of CTU CAN FD is described in:
[![System architecture](](
Functional description of CTU CAN FD is in datasheet:
CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating.
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