- Sep 20, 2024
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Pavel Pisa authored
- pxmc-test-zynq-rvapo: another step to make current calibration work when RVapo is used - Zynq simple DC motor test: updated to build for RTEMS system as well - RPi PXMC Test: updated to build to be prepared for RTEMS build for Zynq - sui_addons/sui_dtreemem: remove remains of dependence on can_vca to build even without it - tools/datavis/pxmc-spimc-currents-show.py: accept even current measurement over single cycle - tools/datavis/pxmc-spimc-currents-show.py: fix compatibility with Python 3 Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Sep 09, 2024
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Pavel Pisa authored
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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Pavel Pisa authored
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Sep 07, 2024
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Pavel Pisa authored
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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Pavel Pisa authored
This allows to fine tune AXI crossbar which is generated by Vivado AXI smartconnect anyway. This way, the crossbar can be tuned to lower FPGA resources utilization considerably. The important lecture, the AXI Thread ID width on Processing System AXI_ACP is 12. It has to be matched by the AXI Thread ID on the corresponding slave port of AXI crossbar. To achieve this, the global AXI Thread ID bits of the AXI crossbar has to be wider by one bit at least to allow mapping of the second slave to the crossbar even that it is not using expedited/threaded transfers. The submodules pxmc-linux and rvapo-vhdl are used at their actual versions. There has been changed RVapo PMSM comprocessor initialization sequence where match between coprocessor firmware and PMSM top level application is required. The application is tested to run on RTEMS as well. CTU CAN FD cores correct mapping and function have been tested on Linux and RTEMS as well. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Jul 04, 2024
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Pavel Pisa authored
pxmc-test-zynq-rvapo: adjust HW type name component from z2dcdrv1 to z3pmdrv1_wmcc pxmc-test-zynq-rvapo: add REGSFRQ to allow set sampling frequency from 500 Hz to 5 kHz pxmc-test-zynq-rvapo: fix function under RTEMS, clock_nanosleep works there as well now Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Jul 02, 2024
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Pavel Pisa authored
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Jun 18, 2024
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Pavel Pisa authored
The data placement corresponds to RVapo project from 2024-06-19 https://gitlab.fel.cvut.cz/otrees/fpga/rvapo-vhdl commit 64cdaac7782cefecf350749b2949f7a0642f8a29 Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Jun 12, 2024
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Gruncl, Damir authored
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- Jun 11, 2024
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Pavel Pisa authored
The top.tcl update/editing in Vivado should be finished by double-click to the block design and run File -> Export -> Export Block Design... Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- Jun 10, 2024
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Pavel Pisa authored
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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- May 28, 2024
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Gruncl, Damir authored
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- May 24, 2024
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Gruncl, Damir authored
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- May 09, 2024
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Gruncl, Damir authored
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Gruncl, Damir authored
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- May 05, 2024
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Gruncl, Damir authored
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Gruncl, Damir authored
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Gruncl, Damir authored
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Gruncl, Damir authored
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- May 04, 2024
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Gruncl, Damir authored
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Gruncl, Damir authored
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Gruncl, Damir authored
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- May 03, 2024
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Gruncl, Damir authored
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