- May 27, 2016
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Martin Jeřábek authored
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- May 06, 2016
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Martin Jeřábek authored
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- Apr 25, 2016
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Apr 22, 2016
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Apr 21, 2016
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Apr 20, 2016
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Martin Jeřábek authored
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- Apr 18, 2016
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Apr 13, 2016
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Apr 12, 2016
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Martin Jeřábek authored
- user LEDS: XOR gate changed to buffer gate - power: fixed diode direction - JX: I/O remapped - universal D-SUB footprints (both straight and angled) - PCB layout: footprints positioned (almost)
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Apr 11, 2016
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Martin Jeřábek authored
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- Apr 10, 2016
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Martin Jeřábek authored
- LM2676 used as main regulator - VCCIO reg feedback voltage divider changed - added capacitors voltage - footprint assignment
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Martin Jeřábek authored
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Martin Jeřábek authored
- I/O (LEDs, KEYs, SWs, CANs, connectors) connected to headers, created according pin assignment file for Vivado - CAN termination moved, fixed common CAN termination - added D-SUB connector footprints JX headers: - removed as submodule, added directly - footprint origin moved to center to allow positioning - pin types changed to enable ERC Power: - VCCIO regulator changed to TPS62260DDC, also included variant with MCP16301 - added testpoints to power outputs and power-good outputs - added jumper JP13 to pull up VCCIO_EN for testing without MicroZed
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- Apr 05, 2016
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Martin Jeřábek authored
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- Mar 15, 2016
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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Martin Jeřábek authored
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- Mar 14, 2016
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Martin Jeřábek authored
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- Mar 04, 2016
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Pavel Pisa authored
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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