Gate level simulation
Currently, GHDL does not support Verilog, nor does Vivado support exporting VHDL timing netlist with VITL. Therefore timing gate level simulation is not really possible... However, Vivado should support VHDL models of FPGA cells via "unisim" library. This should be unit delay simulation.
Following approach might be good:
- Run Synthesis during "build" phase. Will be done in #212 (closed) .
- Export netlist in VHDL/EDIF format to "test" phase.
- Have one test configuration (mix of feature, compliance runs), which will run tests on gates.