Automatization of resource benchmarks
Since the outcome of synthesis is highly dependant on tool settings, FPGA family etc..., the best result from area/performance point of view must be often hand-tuned. Actually, there exists only Benchmark project and set of constraints for evaluation. This is not enough.
This task aims at creating automatized FPGA synthesis scripts for both Xilinx and Intel Families.
General flow of automatic script should be like so:
- Create project from sources. Avoid explicit reference, add all files in "src" folder.
- Load constraints for Xilinx or Intel. Avoid explicit paths, preffer usage of "type" constraint.
- Configure synthesis settings, preffer forbidding hierarchy flattening. Configure synthesis out of context.
- Run synthesis and post-synthesis optimization.
- Export Netlist in VHDL/Verilog/EDIF format.
- Export "Design checkopoints" or "IP-Wrapper" or what the hell it is called on Intel devices...
- Run timing analysis on post-synthesis netlist. Verify that it passed and there are no negative slacks.
- Export Maximum operating frequency and number of used resources in the netlist.