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Created with Raphaël 2.2.020Mar1925Nov1527Apr319Feb21Nov11Apr1028Mar25131152128Feb18151412Jun723May19109527Apr23207530Mar2923191815Add new filemastermasterAdd new directoryAdd new fileAdd new filekimdawon-master…kimdawon-master-patch-02133seminaries/qtrvsim/qtrvsim-semstart: copy from QtRVSimseminaries/qtrvsim/uart-echo-irq: ensure to stay in machine mode after mret testseminaries/qtrvsim/uart-echo-irq: minor update to build by internal assemblereminaries/qtrvsim/call-syscall: example with arguments which exceed to stackseminaries/qtrvsim/call-syscall: add examples matching the lecture.qtrvsim/fibo-hazards: add notice that la use is problematicseminaries/hello-apo: correct .gitignore filename spellingseminaries/hello-apo: Multi-ISA Hello World example for Computer Architecturesseminaries/qtrvsim/os-emu-example: remap open(at) flags to kernel from library defined onesseminaries/qtrvsim/os-emu-example: initial version of C library use example.seminaries/qtrvsim/uart-echo-irq: example from lecture 9 external events.seminaries/qtrvsim/uart-calc-add: task to receive two decimal numbers from UART and send sum in decimal to the UART.seminaries/qtrvsim/print-hex-to-uart: prepared RISC-V version of this task as well.seminaries/qtrvsim/fibo-hazards: remove warning notice, set no hazard unit is already possible in CLI.seminaries/qtrvsim/fibo-hazards: Update rest of the template texts for RISC-V.qtrvsim/fibo-hazards: RISC-V version of the task to resolve data hazards in software.Merge branch 'dupakjak-master-patch-93765' into 'master'lw-hazards.S: fix register notation in lwseminaries/qtrvsim/hazards-from-lecture: examples from lecture 5 pipeline.qtrvsim/apo-sort: RISC-V version of the task to tune cache and program together.seminaries/qtrvsim/selection-sort: add test program for cache tutorialseminaries/qtrvsim: ffs-as-log2 comment final catch loop.seminaries/qtrvsim/bubble-sort: provided template for bubble sort implementation.seminaries/qtrvsim: add ffs-as-log2, the fisrt motivation example from lecture.seminaries/binrep/qtrvsim_binrep: add libgcc.a to the final executable link.seminaries/sum2vars/sum2vars-asm: add RISC-V variant/seminaries/sum2vars/sum2vars-python: rename sum2vars.py to match other languagesseminaries/qtrvsim: update vect-add2 and vect-inc for RISC-V as well.seminaries/qtrvsim: add RISC-V vect-add example variantseminaries/qtrvsim: rename template directory to qtrvsim_template to match architecture.seminaries/binrep/qtrvsim_binrep: RISC-V version of the binary representation exampleseminaries/qtrvsim/qtmips_template: template for RISC-V assembly exercisesseminaries/mzapo/lcd/mzapo_lcdip: add reset parameter to cause LCD controller HW reset.seminaries/qtmips/os-emu-example: example and template for QtMips projects using C library.seminaries/mzapo/lcd/mzapo_lcdip: fix initial IP address value to indicate when no address is offered.seminaries/qtmips/call-syscall/lec10-05-call-6args.S: correct naming to match video.