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Reg automation

Ille, Ondrej, Ing. requested to merge reg_automation into master

Added generation of the Register map documentation. Replaced the memory maps with only 8 bit register map, all VHDL sources modified accordingly. Sanity test is passing with wrapper created by Martin Jeřábek. Minor changes in TCL paths had been modified..

The docu is not yet generated, but the code is prepared for it.

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