Optimizations for better coverage
The coverage analysis executed with VCS during verification towards v2.5 revealed potential design optimizations to reduce number of unreachable coverage bins in various blocks.
This is a tracking issue to work on these.
The main point is to optimize the code in a way where too generic design patterns cause lot of unreachable code to be generated. This leads to requirement for tedious exclude files if high coverage numbers are needed.
Following design patterns causing unreachable design were identified:
-
Reduce width of counters in Prescaler based on value they can count up-to the most. This affects, segment counter, prescaler, extension, etc... See from v2.5 exclude file. -
Split Protocol control FSM into two FSMs: Protocol control and Error transmission. Error transmission FSM would handle Error Active/Passive Flag transmission, as well as moving to "integration" state upon Error condition in ROM mode. A Protocol control FSM would have a single state, that would indicate that the control over the transmission is passed to Error transmission FSM. Once error transmission FSM would be over doing its job, it would signal back to Protocol Control FSM. This would drastically reduce number of available FSM transitions in FSM coverage. -
Rework "Access signaller" in generated register map. Current approach is waaay to generic. Split the access signaller to "Read" and "Write" -
Rework Data MUX in the generated register map. Current approach, where all read data are concatenated to one large vector and padded by zeroes, causes that there is way too many toggles that are constant driven. It is very tedious to do the coverage analysis then. Also, VCS with SX license does not provide the option to automatically exclude constant driven items. So, it would be better to generate non-generic data mux module that would have all register values brought in as ports, and the register selection would be done inside of the generated data mux. Padding by zeroes then could be done in the process that would mux the registers to "data_out" signal. This would get rid of many uncoverable toggles. -
Rework the way that Protocol control FSM gives signals to TXT Buffers. Currently, txtb_hw_cmd
hasunlock
that is active together with either offailed
,error
orarbl
. Due to the design of next state decoder in protocol control FSM, and encoding oftxtb_hw_cmd
, there are unreachable expressions and branches in the TXT Buffer FSM. -
Split Odd and Even TXT Buffer implementation into a separate files. Even TXT Buffers can never be Backup Buffers, and thus they can never be skipped during TXT Buffer Backup mode operation. Thus there is lot of unreachable logic that needed to be waived. -
Make only MSB of init vector configurable via port in crc_calc
.