xilinx ise-14.7 reports of Gated clock - build is attempt to setup NuttX driver development on LX_CPU (LPC4088 + XC6SLX9)
The Xst reports
WARNING:PhysDesignRules:372 - Gated clock. Clock net
can_fd_instances_for[0].can_fd_inst/bus_sampling_inst/bit_err_detector_inst/r
es_n_inv is sourced by a combinatorial pin. This is not good design practice.
Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
can_fd_instances_for[0].can_fd_inst/can_core_inst/fault_confinement_inst/faul
t_confinement_fsm_inst/fc_fsm_res_q_inv is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
More investigation of troubles found on this old tool-chain is ongoing.
Project build with minimal configuration successfully, frames are sent but acknowledge from other side is weak, works when XCAN is used but when another CTU CAN FD or CAN to USB converter are used then transmission fails. Reception is not successful too.
Setup has chance to easily test CTU CAN FD with NuttX and have environment for NuttX driver development because PiKRON's LX_CPU support is included in NuttX mainline.