Modelsim don't ignore PSL assertions in VHDL code
I tried to compile core in ModelSim - INTEL FPGA STARER EDITION 2020.1 and it seems that PSL assertions are not ignored.
** Error: ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/can_top_level.vhd(1035): syntax error, unexpected "IDENTIFIER", expecting ';' ** Error: ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/can_top_level.vhd(1046): near "txtb_asr_gen": An embedded PSL statement may not be separated by a non-comment statement.
Another affected files:
Compile of can_top_level.vhd failed with 2 errors.
Compile of txt_buffer_fsm.vhd failed with 1 errors.
Compile of tx_arbitrator.vhd failed with 2 errors.
Compile of rx_buffer_fsm.vhd failed with 1 errors.
Compile of rx_buffer.vhd failed with 4 errors.
Compile of trigger_generator.vhd failed with 2 errors.
Compile of rx_shift_reg.vhd failed with 1 errors.
Compile of protocol_control_fsm.vhd failed with 1 errors.
Compile of protocol_control.vhd failed with 2 errors.
Compile of operation_control.vhd failed with 2 errors.
Compile of err_counters.vhd failed with 2 errors.
Compile of crc_calc.vhd failed with 2 errors.
Compile of can_core.vhd failed with 2 errors.
Compile of bus_traffic_counters.vhd failed with 2 errors.
Compile of bit_destuffing.vhd failed with 2 errors.
Compile of tx_data_cache.vhd failed with 2 errors.