seminaries/qtrvsim/branchpred-1: add C code in comment

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

seminaries/qtrvsim/branchpred-1/.gitignore

+*.o
+*.srec
+depend
+branchpred-1
+

seminaries/qtrvsim/branchpred-1/Makefile

+ARCH=riscv64-unknown-elf
+#ARCH=riscv64-linux-gnu
+
+SOURCES = branchpred-1.S
+TARGET_EXE = branchpred-1
+
+SOURCES += branchpred-1.S
+LOADLIBES += -lc
+
+CC=$(ARCH)-gcc
+CXX=$(ARCH)-g++
+AS=$(ARCH)-as
+LD=$(ARCH)-ld
+OBJCOPY=$(ARCH)-objcopy
+
+ARCHFLAGS += -mabi=ilp32
+ARCHFLAGS += -march=rv32im
+ARCHFLAGS += -fno-lto
+
+#ARCHFLAGS += -mabi=lp64
+#ARCHFLAGS += -march=rv64imac
+
+CFLAGS  += -ggdb -Os -Wall
+CXXFLAGS+= -ggdb -Os -Wall
+AFLAGS  += -ggdb
+LDFLAGS += -ggdb
+LDFLAGS += -nostartfiles
+LDFLAGS += -nostdlib
+LDFLAGS += -static
+#LDFLAGS += -specs=/opt/musl/riscv64-linux-gnu/lib/musl-gcc.specs
+
+LOADLIBES += -lgcc
+
+CFLAGS  += $(ARCHFLAGS)
+CXXFLAGS+= $(ARCHFLAGS)
+AFLAGS  += $(ARCHFLAGS)
+LDFLAGS += $(ARCHFLAGS)
+
+OBJECTS += $(filter %.o,$(SOURCES:%.S=%.o))
+OBJECTS += $(filter %.o,$(SOURCES:%.c=%.o))
+OBJECTS += $(filter %.o,$(SOURCES:%.cpp=%.o))
+
+all : default
+
+.PHONY : default clean dep all run_test
+
+%.o:%.S
+	$(CC) -D__ASSEMBLY__ $(AFLAGS) -c $< -o $@
+
+%.o:%.c
+	$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
+
+%.o:%.cpp
+	$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $<
+
+%.s:%.c
+	$(CC) $(CFLAGS) $(CPPFLAGS) -S $< -o $@
+
+default : $(TARGET_EXE)
+#default : run_test
+
+$(TARGET_EXE) : $(OBJECTS)
+	$(CC) $(LDFLAGS) $^ $(LOADLIBES) -o $@
+
+dep: depend
+
+depend: $(SOURCES) $(glob *.h)
+	echo '# autogenerated dependencies' > depend
+ifneq ($(filter %.S,$(SOURCES)),)
+	$(CC)  -D__ASSEMBLY__ $(AFLAGS) -w -E -M $(filter %.S,$(SOURCES)) \
+	  >> depend
+endif
+ifneq ($(filter %.c,$(SOURCES)),)
+	$(CC) $(CFLAGS) $(CPPFLAGS) -w -E -M $(filter %.c,$(SOURCES)) \
+	  >> depend
+endif
+ifneq ($(filter %.cpp,$(SOURCES)),)
+	$(CXX) $(CXXFLAGS) $(CPPFLAGS) -w -E -M $(filter %.cpp,$(SOURCES)) \
+	  >> depend
+endif
+
+clean:
+	rm -f *.o *.a $(OBJECTS) $(TARGET_EXE) depend
+
+run_test: $(TARGET_EXE)
+	qtrvsim_cli --pipelined \
+		--dump-cycles $< \
+		--serout serial_port.out
+
+#		--serin serial_port.in \
+
+-include depend

seminaries/qtrvsim/branchpred-1/branchpred-1.S

+.globl _start
+
 # i = s0, j = s1, c = s2, t0 = outer loop limits, t1 = inner loop limit, t3 - auxiliary variable
+# c, i, j = 0; do { do { c++ } while(++j < 5) } while(i < 4);
 
-  addi s1, zero, 0     # c = 0;
-  addi t0, zero, 4     # t0 = 4;
-  addi t1, zero, 5     # t1 = 2
+_start:
+  addi s2, zero, 0   # c = 0; total loop count 
+  addi t0, zero, 4   # t0 = 4; outer loop limit
+  addi t1, zero, 5   # t1 = 5; inner loop limit
 
-  addi s0, zero, 0     # i = 0;
+  addi s0, zero, 0   # i = 0; outer loop inc
 L1:
-  addi s1, zero, 0     # j = 0;
+  addi s1, zero, 0   # j = 0; inner loop inc
 L2:
   addi s2, s2, 1     # c++;