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The actual most active project is integration of 2x [CTU CAN FD Core](https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core), 2x [FD tol OpenCores CAN](https://gitlab.fel.cvut.cz/canbus/zynq/sja1000-fdtol) (SJA1000) and [Zlogan](https://github.com/eltvor/zlogan/) logic analyzer in the design running on on the [PiKRON](http://pikron.com/) [MZ_APO](https://cw.fel.cvut.cz/b182/courses/b35apo/documentation/mz_apo/start) baseboards designed for [MicroZed](http://zedboard.org/product/microzed) SBC to support [Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo/start) course .
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The complete source of mechanics design and electronics boards of the education kit are available from repository [https://gitlab.com/pikron/projects/mz_apo/microzed_apo](https://gitlab.com/pikron/projects/mz_apo/microzed_apo).
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### CAN-BENCH Board and Design
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A bachelor theses of Martin Jeřábek: FPGA Based CAN Bus Channels Mutual Latency Tester and Evaluation, 2016
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