Merge Requests · canbus / CTU CAN FD IP Core · GitLab

WIP: Resolve "TX buffer into SRAM"

!4 · opened Dec 05, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- CLOSED
- 0
updated Dec 05, 2017
WIP: Resolve "Serilize the receive data in the Protocol controller"

!1 · opened Nov 30, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- CLOSED
- 0
updated Nov 30, 2017
WIP: Resolve "Feature test clock tolerance"

!137 · opened Aug 30, 2018 by Ille, Ondrej, Ing. Test maintenance Release 2.1
- CLOSED
- 0
updated Aug 30, 2018
WIP: Resolve "Extend basic unit test run"

!106 · opened Jun 13, 2018 by Ille, Ondrej, Ing. Test maintenance Doing
- CLOSED
- 0
updated Jun 13, 2018
WIP: Resolve "RX buffer unit test"

!102 · opened Jun 08, 2018 by Ille, Ondrej, Ing. Test maintenance
- CLOSED
- 0
updated Jun 08, 2018
WIP: Resolve "RX buffer unit test"

!101 · opened Jun 08, 2018 by Ille, Ondrej, Ing. Test maintenance Doing
- CLOSED
- 0
updated Jun 08, 2018
Resolve "Event logger unit test"

!96 · opened Jun 04, 2018 by Ille, Ondrej, Ing. Test maintenance
- CLOSED
- 0
updated Jun 04, 2018
Resolve "Event logger unit test"

!95 · opened Jun 04, 2018 by Ille, Ondrej, Ing. Test maintenance
- CLOSED
- 0
updated Jun 04, 2018
Resolve "Prescaler unit test"

!88 · opened Jun 02, 2018 by Ille, Ondrej, Ing. Test maintenance
- CLOSED
- 0
updated Jun 02, 2018
Resolve "Protocol control unit test"

!84 · opened May 29, 2018 by Ille, Ondrej, Ing. Test maintenance
- CLOSED
- 0
updated May 29, 2018
Resolve "TX Arbitrator pipeline + Hazard unit"

!81 · opened May 25, 2018 by Ille, Ondrej, Ing. Test maintenance
- CLOSED
- 0
updated May 25, 2018
WIP: Resolve "Add SSP_CFG support to CAN test library"

!222 · opened Feb 16, 2019 by Ing. Viktor Fúra Test improvements
- CLOSED
- 0
updated Feb 19, 2019
Pci driver+without vhdl 2008 trial to start automatic testing

!182 · opened Jan 06, 2019 by Pavel Pisa
- CLOSED
- 0
updated Jan 06, 2019
Merge PCI express support implementation in CTU CAN FD driver

!178 · opened Jan 03, 2019 by Pavel Pisa
- CLOSED
- 0
updated Jan 03, 2019
WIP: Resolve "Design decoupling"

!174 · opened Dec 30, 2018 by Ille, Ondrej, Ing. ISO optimizations
- CLOSED
- 0
updated Dec 30, 2018
WIP: Resolve "Extend pyxact generator with VHDL access generation"

!168 · opened Oct 06, 2018 by Ille, Ondrej, Ing. Wishlist
- CLOSED
- 0
updated Oct 06, 2018
Resolve "TXBHCI is triggered on wrong state transitions"

!136 · opened Aug 30, 2018 by Ille, Ondrej, Ing.
- CLOSED
- 0
updated Aug 30, 2018
WIP: Resolve "RX Buffer commands filtration"

!124 · opened Jul 10, 2018 by Ille, Ondrej, Ing. Bug fixing Doing
- CLOSED
- 0
updated Jul 10, 2018
WIP: Resolve "Reference test problem"

!118 · opened Jun 29, 2018 by Ille, Ondrej, Ing. Bug fixing Doing
- CLOSED
- 0
updated Jun 29, 2018
WIP: Resolve "Fix ALC"

!98 · opened Jun 06, 2018 by Ille, Ondrej, Ing. Bug fixing Doing
- CLOSED
- 0
updated Jun 06, 2018