Re-work SSP shift register to a counter
Modify SSP shift register to counter. This will work like so:
- Counter starts upon first entrance of Data Sample point to original SSP shift register. (First entrance after switching to Secondary Sampling)
- When counter elapses, this creates first "secondary sample".
- Each next sample is then delayed by amount of "Bit time" since the distance between two Secondary Sample Points is equal to length of Bit time.
The question is how to determine length of Bit time... Adding all the bit time segments and multiplying by Time Quanta is not very efficient.
It could be done like so:
- Between r0 and BRS bits there will be another measurement (could be on the same counter!) which will measure length between two sample points. This will be stored in separate register and used as delay value. This is OK, since there is definitely no re-synchronisation between r0 and BRS.