Open
Milestone
ISO optimizations
Collection of tasks which should lead to higher decomposition of the design in order to pass ISO conformance testing without ugly work-arounds.
Unstarted Issues (open and unassigned)
8
Ongoing Issues (open and assigned)
1
Completed Issues (closed)
23
- Sampling and Bit Error detection modularization
- Event Logger: Add message filter results
- Create DLC decoder entity
- Re-work SSP shift register to a counter
- Add Secondary sampling point to Status Bus
- CAN address dependency
- Retransmission counter clear
- FIFO watermark
- Split MODE, SETTINGS, COMMAND, STATUS register
- Align TIMESTAMP to 64 bit Address
- Regmap gen saturation fix.
- Reset of memory registers
- CAN FD TX Bit Error detection optimization
- Documentation clarification - register modifications.
- after transmitting a Passive Error Frame, the node does not transmit Suspend Transmission
- Add VHDL configurations
- Prescaler FSM rework
- add registers for reading current timestamp
- Design decoupling
- SSP offset
- TX Buffer explicit memory
- swap set/reset priority for DOI
- Generate VHDL registers from IP-XACT
