Open
Milestone
ISO optimizations
Collection of tasks which should lead to higher decomposition of the design in order to pass ISO conformance testing without ugly work-arounds.
Unstarted Issues (open and unassigned)
3
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
44
- Fix TX/RX simultaneous trigger
- Prescaler bug-fixes
- Non-synchronisation on dominant transmitted bit
- Fix REC decrement
- Fix Overload delimiter lenght
- Fix active error overload flag signalling
- Edge based EWL Interrupt
- Remove CAN ID from can_top_level.
- Stuff counter when SOF is not transmitted
- TX Arbitrator - extend arbitration
- Synchronization edge by Time Quanta
- Set Abort + Retransmitt counter
- Block BTR and BTR_FD during operation
- TXT Buffer changed handling
- Event Logger removal
- ISO compliant SSP config
- Sampling and Bit Error detection modularization
- Event Logger: Add message filter results
- Create DLC decoder entity
- Re-work SSP shift register to a counter
- Add Secondary sampling point to Status Bus
- CAN address dependency
- Retransmission counter clear
- FIFO watermark
- Split MODE, SETTINGS, COMMAND, STATUS register
- Align TIMESTAMP to 64 bit Address
- Regmap gen saturation fix.
- Reset of memory registers
- CAN FD TX Bit Error detection optimization
- Documentation clarification - register modifications.
- after transmitting a Passive Error Frame, the node does not transmit Suspend Transmission
- Config options on top
- Add configurable reset
- Add VHDL configurations
- Prescaler FSM rework
- add registers for reading current timestamp
- Design decoupling
- SSP offset
- Protocol exception behaviour
- TX Buffer explicit memory
- Protocol Control rework
- swap set/reset priority for DOI
- Generate VHDL registers from IP-XACT
- Overload frame
