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CTU CAN FD IP Core
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Updated date
Resolve "Stuff counter when SOF is not transmitted"
!263
· created
Oct 07, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Nov 29, 2019
Resolve "Re-work SSP shift register to a counter"
!283
· created
Nov 07, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Rejected
Merged
0
updated
Nov 07, 2019
Resolve "Edge based EWL Interrupt"
!269
· created
Oct 16, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Oct 16, 2019
src: Fix, only active error flag should be considered.
!266
· created
Oct 09, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Oct 09, 2019
src,test: Remove obsolete CAN ID from can_top_level.
!265
· created
Oct 09, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Oct 09, 2019
Resolve "TX Arbitrator - extend arbitration"
!258
· created
Oct 02, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Oct 05, 2019
Resolve "Protocol Control rework"
!247
· created
Jun 22, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Aug 04, 2019
Resolve "Prescaler FSM rework"
!242
· created
Mar 19, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Mar 22, 2019
src: Remove explicit architectures
!241
· created
Mar 18, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Mar 18, 2019
Resolve "CAN address dependency"
!240
· created
Mar 18, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Mar 18, 2019
Resolve "Sampling and Bit Error detection modularization"
!230
· created
Feb 28, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
7
updated
Mar 09, 2019
Resolve "Create DLC decoder entity"
!228
· created
Feb 25, 2019
by
Ing. Viktor Fúra
ISO optimizations
Merged
0
updated
Feb 26, 2019
design: Add NBT,DBT and SEC sample points delayed by 1 clock.
!221
· created
Feb 08, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Feb 08, 2019
Resolve "Split MODE, SETTINGS, COMMAND, STATUS register"
!218
· created
Feb 02, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
1
updated
Feb 04, 2019
design: replace tx_data shift reg with fifo cache.
!202
· created
Jan 18, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Jan 18, 2019
Resolve "Align TIMESTAMP to 64 bit Address"
!195
· created
Jan 10, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Jan 10, 2019
Resolve "Regmap gen saturation fix."
!192
· created
Jan 08, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Jan 08, 2019
Added explicit warning to register descriptions. Some registers are
!185
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
4
updated
Jan 06, 2019
SRC REGISTERS Fixed reset.
!187
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Jan 06, 2019
Resolve "SSP offset"
!183
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Jan 06, 2019
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