Skip to content
GitLab
Explore
Sign in
Open
0
Merged
20
Closed
7
All
27
Recent searches
{{ formattedKey }}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Popularity
Resolve "Unify "others" clause!"
!129
· created
Jul 13, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jul 13, 2018
Resolve "Bus off time"
!127
· created
Jul 12, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jul 12, 2018
Resolve "TODO research"
!126
· created
Jul 10, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jul 10, 2018
Resolve "RX Buffer commands filtration"
!125
· created
Jul 10, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jul 10, 2018
Resolve "Fix the DLC reception"
!123
· created
Jul 10, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jul 10, 2018
Resolve "Add sync. chain attributes."
!121
· created
Jul 09, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jul 09, 2018
Resolve "Reference test problem"
!119
· created
Jun 29, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jun 29, 2018
Resolve "TXT Buffer in bus-off"
!117
· created
Jun 28, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jun 28, 2018
Resolve "ipyxact_parser is checked in as a submodule, but not declared in .gitmodules"
!100
· created
Jun 06, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jun 06, 2018
Resolve "Remove obsolete config options"
!94
· created
Jun 02, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jun 02, 2018
Resolve "Hard sync in the EDL"
!86
· created
May 31, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
May 31, 2018
Resolve "Buffer Data endianess"
!70
· created
May 19, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
May 19, 2018
Resolve "Endian fix"
!69
· created
May 19, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
May 19, 2018
Resolve "Software reset via MODE[RST] should reset the whole core"
!62
· created
Apr 24, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Apr 24, 2018
Resolve "Transceiver delay"
!60
· created
Apr 20, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Apr 20, 2018
Resource optimizations
!21
· created
Jan 02, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Jan 02, 2018
Resource optimizations
!14
· created
Dec 13, 2017
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Dec 13, 2017
Added bit-rate switch compensation of Ph2 segment
!13
· created
Dec 12, 2017
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Dec 12, 2017
Renamed registers entity to "canfd_registers"
!12
· created
Dec 12, 2017
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Dec 12, 2017
Resource optimizations
!10
· created
Dec 11, 2017
by
Ille, Ondrej, Ing.
Bug fixing
Merged
updated
Dec 11, 2017