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CTU CAN FD IP Core
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Label priority
Resolve "Source code decoupling"
!353
· created
Aug 22, 2020
by
Ille, Ondrej, Ing.
Test improvements
Closed
0
updated
Aug 22, 2020
WIP: Resolve "driver: updates based on v4 patches review"
!351
· created
Aug 15, 2020
by
Pavel Pisa
Closed
0
updated
Aug 15, 2020
Resolve "VHDL 93 with Vivado compatibility troubles: rx_triggers cannot read from output"
!343
· created
Jul 22, 2020
by
Ille, Ondrej, Ing.
ISO optimizations
Closed
0
updated
Jul 22, 2020
WIP: Resolve "Improve readme"
!327
· created
Jan 13, 2020
by
Ille, Ondrej, Ing.
Closed
0
updated
Jan 13, 2020
WIP: Resolve "Update Vivado component after top level component change to can_top_apb"
!290
· created
Nov 09, 2019
by
Pavel Pisa
Closed
0
updated
Nov 09, 2019
WIP: Resolve "Update Vivado component after top level component change to can_top_apb"
!289
· created
Nov 09, 2019
by
Pavel Pisa
Closed
0
updated
Nov 09, 2019
WIP: Resolve "Update Vivado component after top level component change to can_top_apb"
!288
· created
Nov 09, 2019
by
Pavel Pisa
Closed
0
updated
Nov 09, 2019
WIP: Resolve "Split driver into OF and PCI modules"
!287
· created
Nov 09, 2019
by
Jaroslav Beran
Closed
0
updated
Nov 12, 2019
test: Use only single thread to see if coverage will get better!
!286
· created
Nov 08, 2019
by
Ille, Ondrej, Ing.
Closed
0
updated
Jan 03, 2020
WIP: Resolve "Missing TX spinlock release leads to deadlock"
!275
· created
Oct 25, 2019
by
Jaroslav Beran
Closed
0
updated
Oct 28, 2019
WIP: Resolve "Component for Quartus / Platform Designer (Qsys)"
!274
· created
Oct 25, 2019
by
Jaroslav Beran
Closed
0
updated
Oct 28, 2019
WIP: Resolve "Component for Quartus / Platform Designer (Qsys)"
!271
· created
Oct 19, 2019
by
Pavel Pisa
Closed
0
updated
Oct 25, 2019
WIP: Resolve "Add driver doc to gitlab"
!260
· created
Oct 06, 2019
by
Ille, Ondrej, Ing.
Closed
0
updated
Oct 06, 2019
WIP: Resolve "Update Quartus CAN_Wrapper to match core after 194-protocol-control-rework."
!251
· created
Aug 03, 2019
by
Pavel Pisa
Closed
0
updated
Aug 03, 2019
WIP: Resolve "reduce log size"
!248
· created
Aug 03, 2019
by
Ille, Ondrej, Ing.
Closed
0
updated
Aug 03, 2019
WIP: Resolve "Add SSP_CFG support to CAN test library"
!222
· created
Feb 16, 2019
by
Ing. Viktor Fúra
Test improvements
Closed
0
updated
Feb 19, 2019
Pci driver+without vhdl 2008 trial to start automatic testing
!182
· created
Jan 06, 2019
by
Pavel Pisa
Closed
0
updated
Jan 06, 2019
Merge PCI express support implementation in CTU CAN FD driver
!178
· created
Jan 03, 2019
by
Pavel Pisa
Closed
0
updated
Jan 03, 2019
WIP: Resolve "Design decoupling"
!174
· created
Dec 30, 2018
by
Ille, Ondrej, Ing.
ISO optimizations
Closed
0
updated
Dec 30, 2018
WIP: Resolve "Extend pyxact generator with VHDL access generation"
!168
· created
Oct 06, 2018
by
Ille, Ondrej, Ing.
Wishlist
Closed
0
updated
Oct 06, 2018
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