From 7f84aecd7659f253828473dffd9a776c84182ae3 Mon Sep 17 00:00:00 2001
From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Date: Tue, 15 Feb 2022 02:20:45 +0100
Subject: [PATCH] seminaries/qtrvsim: add RISC-V vect-add example variant
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
---
seminaries/qtrvsim/qtrvsim.url | 2 +
seminaries/qtrvsim/vect-add/.gitignore | 3 +
seminaries/qtrvsim/vect-add/Makefile | 80 +++++++++++++++++++++++
seminaries/qtrvsim/vect-add/vect-add.S | 87 ++++++++++++++++++++++++++
4 files changed, 172 insertions(+)
create mode 100644 seminaries/qtrvsim/qtrvsim.url
create mode 100644 seminaries/qtrvsim/vect-add/.gitignore
create mode 100644 seminaries/qtrvsim/vect-add/Makefile
create mode 100644 seminaries/qtrvsim/vect-add/vect-add.S
diff --git a/seminaries/qtrvsim/qtrvsim.url b/seminaries/qtrvsim/qtrvsim.url
new file mode 100644
index 0000000..8ad5170
--- /dev/null
+++ b/seminaries/qtrvsim/qtrvsim.url
@@ -0,0 +1,2 @@
+https://github.com/cvut/qtrvsim
+
diff --git a/seminaries/qtrvsim/vect-add/.gitignore b/seminaries/qtrvsim/vect-add/.gitignore
new file mode 100644
index 0000000..caa6d79
--- /dev/null
+++ b/seminaries/qtrvsim/vect-add/.gitignore
@@ -0,0 +1,3 @@
+*.o
+depend
+vect-add
diff --git a/seminaries/qtrvsim/vect-add/Makefile b/seminaries/qtrvsim/vect-add/Makefile
new file mode 100644
index 0000000..aa1ec54
--- /dev/null
+++ b/seminaries/qtrvsim/vect-add/Makefile
@@ -0,0 +1,80 @@
+ARCH=riscv64-unknown-elf
+
+SOURCES = vect-add.S
+TARGET_EXE = vect-add
+
+LDFLAGS += -Wl,-Ttext,0x200 -Wl,-Tdata,0x400
+
+
+CC=$(ARCH)-gcc
+CXX=$(ARCH)-g++
+AS=$(ARCH)-as
+LD=$(ARCH)-ld
+OBJCOPY=$(ARCH)-objcopy
+
+ARCHFLAGS += -mabi=ilp32
+ARCHFLAGS += -march=rv32i
+ARCHFLAGS += -fno-lto
+
+CFLAGS += -ggdb -Os -Wall
+CXXFLAGS+= -ggdb -Os -Wall
+AFLAGS += -ggdb
+LDFLAGS += -ggdb
+LDFLAGS += -nostartfiles
+LDFLAGS += -nostdlib
+LDFLAGS += -static
+#LDFLAGS += -specs=/opt/musl/riscv64-linux-gnu/lib/musl-gcc.specs
+
+CFLAGS += $(ARCHFLAGS)
+CXXFLAGS+= $(ARCHFLAGS)
+AFLAGS += $(ARCHFLAGS)
+LDFLAGS += $(ARCHFLAGS)
+
+OBJECTS += $(filter %.o,$(SOURCES:%.S=%.o))
+OBJECTS += $(filter %.o,$(SOURCES:%.c=%.o))
+OBJECTS += $(filter %.o,$(SOURCES:%.cpp=%.o))
+
+all : default
+
+.PHONY : default clean dep all
+
+%.o:%.S
+ $(CC) -D__ASSEMBLY__ $(AFLAGS) -c $< -o $@
+
+%.o:%.c
+ $(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
+
+%.o:%.cpp
+ $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $<
+
+%.s:%.c
+ $(CC) $(CFLAGS) $(CPPFLAGS) -S $< -o $@
+
+default : $(TARGET_EXE)
+
+$(TARGET_EXE) : $(OBJECTS)
+ $(CC) $(LDFLAGS) $^ -o $@
+
+dep: depend
+
+depend: $(SOURCES) $(glob *.h)
+ echo '# autogenerated dependencies' > depend
+ifneq ($(filter %.S,$(SOURCES)),)
+ $(CC) -D__ASSEMBLY__ $(AFLAGS) -w -E -M $(filter %.S,$(SOURCES)) \
+ >> depend
+endif
+ifneq ($(filter %.c,$(SOURCES)),)
+ $(CC) $(CFLAGS) $(CPPFLAGS) -w -E -M $(filter %.c,$(SOURCES)) \
+ >> depend
+endif
+ifneq ($(filter %.cpp,$(SOURCES)),)
+ $(CXX) $(CXXFLAGS) $(CPPFLAGS) -w -E -M $(filter %.cpp,$(SOURCES)) \
+ >> depend
+endif
+
+clean:
+ rm -f *.o *.a $(OBJECTS) $(TARGET_EXE) depend
+
+#mips-elf-objdump --source -M no-aliases,reg-names=numeric qtmips_binrep
+
+-include depend
diff --git a/seminaries/qtrvsim/vect-add/vect-add.S b/seminaries/qtrvsim/vect-add/vect-add.S
new file mode 100644
index 0000000..6bbb5b0
--- /dev/null
+++ b/seminaries/qtrvsim/vect-add/vect-add.S
@@ -0,0 +1,87 @@
+// Directives to make interresting windows visible
+#pragma qtrvsim show registers
+#pragma qtrvsim show memory
+
+.option norelax
+
+.globl _start
+
+.text
+
+// int *pa;
+// int *pb;
+// int *pc;
+
+_start:
+main:
+loop:
+ la x5, vect_a // pa = vec_a
+ la x6, vect_b // pb = vec_b
+ la x7, vect_c // pc = vec_c
+ addi x8, x0, 16 // int i = 16
+vect_next: // do {
+ lw x2, 0(x5) // r2 = *pa
+ lw x3, 0(x6) // r3 = *pb
+ add x4, x2, x3 // r4 = r2 + r3
+ sw x4, 0(x7) // *pc = r4
+
+ addi x5, x5, 4 // pa++
+ addi x6, x6, 4 // pb++
+ addi x7, x7, 4 // pc++
+ addi x8, x8, -1 // i--
+ bne x8, x0, vect_next // } while (i != 0)
+
+ // stop execution wait for debugger/user
+ ebreak
+ // ensure that continuation does not
+ // interpret random data
+ beq x0, x0, loop
+
+.bss
+
+.org 0x400
+
+.data
+
+vect_a: // int vect_a[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0};
+ .word 0x01
+ .word 0x02
+ .word 0x03
+ .word 0x04
+ .word 0x05
+ .word 0x06
+ .word 0x07
+ .word 0x08
+ .word 0x09
+ .word 0x0a
+ .word 0x0b
+ .word 0x0c
+ .word 0x0d
+ .word 0x0e
+ .word 0x0f
+ .word 0x00
+
+vect_b: // int vect_b[16] = {16, 32, 48, 64, ...};
+ .word 0x10
+ .word 0x20
+ .word 0x30
+ .word 0x40
+ .word 0x50
+ .word 0x60
+ .word 0x70
+ .word 0x80
+ .word 0x90
+ .word 0xa0
+ .word 0xb0
+ .word 0xc0
+ .word 0xd0
+ .word 0xe0
+ .word 0xf0
+ .word 0x00
+
+vect_c: // int vect_c[16];
+ .skip 64
+
+// Specify location to show in memory window
+#pragma qtrvsim focus memory vect_a
+
--
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