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- Graphical RISC-V Architecture Simulator - Memory Model and Project Management; [Jakub Dupák](https://jakubdupak.com/); 2021; [Bachelor Thesis](https://dspace.cvut.cz/bitstream/handle/10467/94446/F3-BP-2021-Dupak-Jakub-thesis.pdf); [git](https://github.com/cvut/qtrvsim)
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- Graphical RISC-V Architecture Simulator - Instructions Decode and Execution and OS Emulation; Max Hollmann; 2021; [Bachelor Thesis](https://dspace.cvut.cz/bitstream/handle/10467/96707/F3-BP-2021-Hollmann-Max-thesis.pdf)
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- Open Rapid Control Prototyping and Real-Time Systems; Michal Lenc; 2022; [Bachelor Thesis](https://dspace.cvut.cz/bitstream/handle/10467/100938/F3-BP-2022-Lenc-Michal-Open_Rapid_Control_Prototyping_and_Real_Time_Systems.pdf); [silicon-heaven](https://github.com/robertobucher/pysimCoder/wiki/Silicon-Heaven-Support) support for [pysimCoder](https://github.com/robertobucher/pysimCoder), [pysimCoder integration with NuttX](https://nuttx.apache.org/docs/latest/guides/pysimcoder.html)
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- Control and Bluetooth Communication for Wearable Safety Jacket Applications; Ladislav Štefka; 2022; [Master Thesis](https://dspace.cvut.cz/bitstream/handle/10467/101420/F3-DP-2022-Stefka-Ladislav-Stefka_Ladislav_MasterThesis_final.pdf); [git group](https://gitlab.fel.cvut.cz/otrees/blueiotoy), [firmware](https://gitlab.fel.cvut.cz/otrees/blueiotoy/nrf52-apps-sdk)
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- CAN Bus Latency Test Automation for Continuous Testing and Evaluation; Matěj Vasilevski; 2022; [Master Thesis](https://dspace.cvut.cz/bitstream/handle/10467/101450/F3-DP-2022-Vasilevski-Matej-vasilmat.pdf); [project](https://canbus.pages.fel.cvut.cz/), [timestamp patch](https://lore.kernel.org/netdev/20220512232706.24575-1-matej.vasilevski@seznam.cz/) |
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