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...@@ -30,6 +30,10 @@ Design of new hardware. ...@@ -30,6 +30,10 @@ Design of new hardware.
### MZ_APO Xilinx Zynq related projects ### MZ_APO Xilinx Zynq related projects
The project with standard educational peripherals for MZ_APO kits is available there [https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top](https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top) as part [CTU FEE CAN bus](http://canbus.pages.fel.cvut.cz/) related projects.
The description how to build design including two peripherals to connect DC motors to PMOD1 and PMOD2 connectors is described in the project [Wiki](https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/-/wikis/B35APO-Buid-on-MZ_APO)
#### HDL Design of DMA Based Framebuffer Output to Parallel Connected LCD (FA) #### HDL Design of DMA Based Framebuffer Output to Parallel Connected LCD (FA)
#### HDL Design of Interface and Drivers for Stereo CMOS Camera Chips (FA) #### HDL Design of Interface and Drivers for Stereo CMOS Camera Chips (FA)
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