Explore projects

Road and in particular railroad grade (slope) estimation from onboard measurements.

pap-rvapo, but with C instead of Rust, and minor changes to cpu design

Firmware kostky Open-Cube (https://maglab.fel.cvut.cz/open-cube/)

Repository to share code, HDL and project templates and data with students of Advanced Computer Architectures course

MicroZed design with 2x CTU CAN FD Core, 2x FD tol OpenCores CAN (SJA1000) and Zlogan logic analyzer.

CAN with Flexible Data-rate IP Core developed at Department of Measurement of FEE CTU. See the list of related CAN projects and IP core integrations.

RISC-V processor designed in VHDL to match QtRvSim

Web pages of OSY, see http://osy.pages.fel.cvut.cz/.

Zadání domácích úkolů pro předmět Modelování a simulace dynamických systémů.