This document was generated by Kactus2 on 20.04.2018 15:53:33 by user

Table of contents
1. Component CTU - ip - CAN_FD_IP_Core - 2.1
   1.1. Kactus2 attributes
   1.2. Memory maps

1. Component CTU - ip - CAN_FD_IP_Core - 2.1

CTU - ip - CAN_FD_IP_Core - 2.1 preview picture
Description: CAN FD IP Core from Ondrej Ille written at Czech Technical University, department of Measurement.
IP-Xact file: CAN_FD_IP_Core.2.1.xml

1.1 Kactus2 attributes

   Product hierarchy: IP
   Component implementation: HW
   Component firmness: Mutable

1.2 Memory maps

1.2.1 Regs

   Description: CTU CAN FD IP Core is designed as 32 bit peripheria with byte enable support for 8, 16 or 32 bit access. Unaligned access is not supported. Byte or half word access is executed via byte enable signal. The memory is organized as Big endian. Write to read only memory location will have no effect. Read from write only memory location will return zeroes. The memory map consists of following memory regions:
   Address unit bits (AUB): 8

1.2.1.1 Control_registers

   Description: Control registers memory region.

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
register 'h0 256 32 true

1.2.1.1.1 DEVICE_ID

   Description: Register contains the identifer of CAN FD IP function. It can be used to determine if CAN IP function is mapped correctly on its base address.

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 16 0 true read-only

Register DEVICE_ID contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
DEVICE_ID 0 16 read-only 'hCAFD Device ID

1.2.1.1.2 MODE

   Description: MODE register controls operating modes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 8 0 true read-write

Register MODE contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RST 0 1 0 Writing logic 1 resets the core. It has the same effect as logic 0 on "res_n" input of the controller.
FDE 4 1 1 Enable flexible data rate support. When disabled, receiving recessive EDL bit (Flexible data-rate frame) causes Form error. This bit does not affect capability to transmitt FD Frames.
TSM 6 1 0 Tripple sampling mode. Bus value is sampled three times when this mode is enabled. Even if this bit is set, triple sampling is used only during Nominal data rate. CAN standard reccomends to use tripple sampling at low Bit rates.
RTR_PREF 5 1 1 RTR Frame preferred behavior. When RTR frame is sent non-zero dlc code can be inserted. This bit specifies the behavior of controller when sending RTR Frames.
ACF 7 1 0 Acknowledge forbidden mode. When this mode is enabled, acknowledge is not sent even if received CRC matches the calculated one.
LOM 1 1 0 Listen only mode. In this mode controller only receives data and sends only recessive bits on the bus. When a dominant bus is sent it is rerouted internally so that bus value remains the same. Note that when this mode is enabled controller will not transmit any inserted frame!
STM 2 1 0 Self test mode. In this mode transmitted frame is considered valid even if acknowledge was not received.
AFM 3 1 0 Acceptance filters mode. If this mode is enabled, acceptance filters are used on RX Frames . If disabled, every received frame is stored in the RX buffer. This bit has meaning only if there is at least one filter synthesized.

1.2.1.1.3 COMMAND

   Description: Writing logic 1 into each bit gives different command to the IP Core. After writing logic 1, logic 0 does not have to be written.

Offset [AUB] Size [bits] Dimension Volatile Access
'h5 8 0 true writeOnce

Register COMMAND contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
AT 1 1 0 Abort transmission of CAN frame. CTU CAN FD IP Core will immediately move to the Interframe state. If the Core is a receiver, this command has no effect. Aborting transmission can be used to release the bus immediately. If another unit is receiving frame whose transmission is aborted, it will start transmitting Error frame due to Stuff Error. TXT Buffer will move to TX Error state.
RRB 2 1 0 Release Receive buffer. This command deletes all data from the Receive buffer and restarts its memory pointers.
CDO 3 1 0 Clear data overrun flag. This command will clear data overrun flag on RX Buffer.

1.2.1.1.4 STATUS

   Description: Register signals various states of CTU CAN FD IP Core. Logic 1 signals active state/flag.

Offset [AUB] Size [bits] Dimension Volatile Access
'h6 8 0 true read-only

Register STATUS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RBS 0 1 0 Receive buffer is not empty.
TBS 2 1 0 TXT buffer status. Active if at least one of the TXT Buffers is in "Empty" state.
DOS 1 1 0 Data overrun status (flag). A frame was lost due to insufficient space in the Receive buffer. This bit can be cleaned by CDO command.
ET 3 1 0 Error frame is beeing transmitted at the moment.
RS 4 1 0 CTU CAN FD IP Core is a receiver of CAN Frame.
TS 5 1 0 CTU CAN FD IP Core is a transmitter of CAN Frame.
ES 6 1 0 Error status. Error warning limit was reached at any of error counters.
BS 7 1 1 Bus status. Bus is "idle", the controller is " integrating" or "bus off". Therefore this bit is active when there is no activity on the bus.

1.2.1.1.5 SETTINGS

   Description: This register enables the whole CAN FD Core, configures FD Type, Internal loopback and retransmission options.

Offset [AUB] Size [bits] Dimension Volatile Access
'h7 8 0 true read-write

Register SETTINGS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RTRLE 0 1 0 Retransmitt limit enable. If enabled, the core only attempts to transmitt each frame up to RTR_TH times. If not succesfull, the TXT Buffer will end up in "Failed" state.
RTR_TH 1 4 0 The maximal amount of retransmission attempts.
INT_LOOP 5 1 0 Internal loop-back option (recommended only for testing). If internal loopback options is enabled the Core automatically receive any dominant bit it transmitts.
ENA 6 1 0 Enable bit for the whole CAN FD Controller. When disabled, IP Core acts as if not connected to the CAN Bus.
FD_TYPE 7 1 0 Selection between two possible CAN FD frame formats.

1.2.1.1.6 INT_STAT

   Description: Reading this register returns Interrupt vector (status of generated Interrupts). Writing logic 1 to any bit clears according interrupt. Writing logic 0 has no effect.

Offset [AUB] Size [bits] Dimension Volatile Access
'h8 16 0 true read-write

Register INT_STAT contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RI 0 1 0 Frame Received interrupt
TI 1 1 0 Frame transceived interrupt
EI 2 1 0 Error warning limit reached interrupt
DOI 3 1 0 Data overrun on RX Buffer Interrupt
EPI 4 1 0 Node became error passive or bus off interrupt
ALI 5 1 0 Arbitration lost interrupt
BEI 6 1 0 Bus Error interrupt
LFI 7 1 0 Event logging finished interrupt
RFI 8 1 0 Receive buffer full interrupt
BSI 9 1 0 Bit-rate shifted interrupt
RBNEI 10 1 0 Receive buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt.
TXBHCI 11 1 0 TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core, this interrupt will be acivated.

1.2.1.1.7 RX_SETTINGS

   Description: Settings register for FIFO RX Buffer.

Offset [AUB] Size [bits] Dimension Volatile Access
'h62 8 0 true read-write

Register RX_SETTINGS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RTSOP 0 1 0 Receive buffer Timestamp option.

1.2.1.1.8 INT_ENA_CLR

   Description: Writing logic 1 disables according interrupt. Writing logic 0 has no effect. Reading this register has no effect.

Offset [AUB] Size [bits] Dimension Volatile Access
'h10 16 0 true write-only

Register INT_ENA_CLR contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
INT_ENA_CLR 0 12 0 Bit meaning is equivalent to register INT_STAT.

1.2.1.1.9 INT_MASK_CLR

   Description: Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect. Reading this register has no effect. Un-masked interrupt is captured, can be read from INT_STAT, and it does affect interrupt output of the CAN Core.

Offset [AUB] Size [bits] Dimension Volatile Access
'h18 16 0 true write-only

Register INT_MASK_CLR contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
INT_MASK_CLR 0 12 'h0 Bit meaning is equivalent to register INT_STAT.

1.2.1.1.10 INT_MASK_SET

   Description: Writing logic 1 masks according interrupt. Writing logic 0 has no effect. Reading this register returns status of the interrupt mask. Masked interrupt is captured, and can be read from INT_STAT, but does not affect interrupt output of the CAN Core.

Offset [AUB] Size [bits] Dimension Volatile Access
'h14 16 0 true read-write

Register INT_MASK_SET contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
INT_MASK_SET 0 12 'h0 Bit meaning is equivalent to register INT_STAT.

1.2.1.1.11 INT_ENA_SET

   Description: Writing logic 1 to a bit enables according interrupt.Writing logic 0 has no effect. Reading the register returns logic 1 in every bit whose interrupt capturing is enabled.

Offset [AUB] Size [bits] Dimension Volatile Access
'hC 16 0 true read-write

Register INT_ENA_SET contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
INT_ENA_SET 0 12 'h0 Bit meaning is equivalent to register INT_STAT.

1.2.1.1.12 BTR_FD

   Description: Bit timing register for data bit-rate.

Offset [AUB] Size [bits] Dimension Volatile Access
'h20 32 0 true read-write

Register BTR_FD contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
PH2_FD 13 5 3 Phase 2 segment
PROP_FD 0 6 3 Propagation segment
PH1_FD 7 5 3 Phase 1 segment
BRP_FD 19 8 4 Baud-rate prescaler
SJW_FD 27 5 2 Synchronisation jump width

1.2.1.1.13 VERSION

   Description: Version register with IP Core version.

Offset [AUB] Size [bits] Dimension Volatile Access
'h2 16 0 true read-only

Register VERSION contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
VER_MINOR 0 8 Minor part of the IP Core version. E.g for version 2.1 this field has value 0x01.
VER_MAJOR 8 8 Minor part of the IP Core version. E.g for version 2.1 this field has value 0x02.

1.2.1.1.14 BTR

   Description: Bit timing register for nominal bit-rate.

Offset [AUB] Size [bits] Dimension Volatile Access
'h1C 32 0 true read-write

Register BTR contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
PROP 0 7 5 Propagation segment
PH1 7 6 3 Phase 1 segment
PH2 13 6 5 Phase 2 segment
BRP 19 8 'hA Baud-rate prescaler
SJW 27 5 2 Synchronisation jump width

1.2.1.1.15 ALC

   Description: Arbitration lost capture register.

Offset [AUB] Size [bits] Dimension Volatile Access
'h75 8 0 true read-only

Register ALC contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
ALC_VAL 0 5 0 Arbitration lost capture value. Not supported yet. Do not use!

1.2.1.1.16 EWL

   Description: Error warning limit register.

Offset [AUB] Size [bits] Dimension Volatile Access
'h24 8 0 true read-write

Register EWL contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
EWL_LIMIT 0 8 96 Error warning limit. If an error warning limit is reached interrupt can be called. Error warning limit indicates heavily disturbed bus. Note that according to CAN specification this value is fixed at 96 and should not be configurable! The configuration of this value is one of the extra features of this IP Core.

1.2.1.1.17 ERP

   Description: Error passive limit register.

Offset [AUB] Size [bits] Dimension Volatile Access
'h25 8 0 true read-write

Register ERP contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
ERP_LIMIT 0 8 128 Error passive limit. When one of error counters (RXC/TXC) exceeds this value, i Fault confinement state changes to error passive. Note that according to CAN specification this value is fixed at 128 and should not be configurable! The configuration of this value is one of the extra features of this IP Core. Note that IP Core always turns to bus_off state once any error counter reaches 255!

1.2.1.1.18 FAULT_STATE

   Description: Fault confinement state of the node. This state can be manipulated by writes to CTR_PRES register. When these counters are set Fault confinement state changes automatically.

Offset [AUB] Size [bits] Dimension Volatile Access
'h26 16 0 true read-only

Register FAULT_STATE contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
ERP 1 1 0 Error passive
BOF 2 1 0 Bus off
ERA 0 1 1 Error active

1.2.1.1.19 FILTER_A_VAL

   Description: Bit value for acceptance filters. Filters A, B, C are available. The identifier format is the same as transmitted and received identifier format. BASE Identifier is 11 LSB and Identifier extension are bits 28-12! Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtX=false";. If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h38 32 0 true read-write

Register FILTER_A_VAL contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_VAL_A_VAL 0 29 0 Bit Value for acceptance filters to be compared with income identifier. Only bits set in according to FILTER_A_MASK register are compared.

1.2.1.1.20 FILTER_STATUS

   Description: This register provides information if the Core is synthesized with fillter support.

Offset [AUB] Size [bits] Dimension Volatile Access
'h56 16 0 true read-only

Register FILTER_STATUS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
SFA 0 1 Logic 1 when the Core was synthesized with "sup_filtA = true" Otherwise logic 0.
SFB 1 1 Logic 1 when the Core was synthesized with "sup_filtB = true" Otherwise logic 0.
SFR 3 1 Logic 1 when the Core was synthesized with "sup_range = true" Otherwise logic 0.
SFC 2 1 Logic 1 when the Core was synthesized with "sup_filtC = true" Otherwise is logic 0.

1.2.1.1.21 TX_PRIORITY

   Description: Priority of the TXT Buffers in TX Arbitrator. Higher priority value signals that buffer is selected earlier for transmission. If two buffers have equal priorities, the one with lower index is selected.

Offset [AUB] Size [bits] Dimension Volatile Access
'h70 16 0 true read-write

Register TX_PRIORITY contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXT1P 0 3 1 Priority of TXT Buffer 1.
TXT2P 4 3 0 Priority of TXT Buffer 2.
TXT3P 8 3 0 Priority of TXT Buffer 3.
TXT4P 12 3 0 Priority of TXT Buffer 4.

1.2.1.1.22 TX_COMMAND

   Description: Command register for TXT Buffers. Command is activated by setting TXC(E,R,A) bit to logic 1. Buffer that receives the command is selected by setting bit TXBI(1..4) to logic 1. Command and index must be set by single access. Register is automatically erased upon the command completion and 0 does not need to be written. Reffer to description of TXT Buffer circuit for TXT buffer State machine.

Offset [AUB] Size [bits] Dimension Volatile Access
'h6C 16 0 true write-only

Register TX_COMMAND contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXCE 0 1 0 Activates "set_empty" command. Transits frone TX Done, TX Error or TX Aborted to Done.
TXCR 1 1 0 Activates "set_ready" command. Transits frone TX Done, TX Error, TX Aborted or Empty to Ready.
TXCA 2 1 0 Activates "set_abort" command. Transits from Ready to TX Aborted. If transmission is in progress (state TX in Progress) from the buffer, transits to TX Aborted if current transmission is not succesfull. If the transmission is sucesfull, it has no effect.
TXI1 8 1 0 Command is applied on TXT Buffer 1.
TXI2 9 1 0 Command is applied on TXT Buffer 2.
TXI3 10 1 0
TXI4 11 1 0

1.2.1.1.23 YOLO_REG

   Description: Register for fun :)

Offset [AUB] Size [bits] Dimension Volatile Access
'h88 32 0 true read-only

Register YOLO_REG contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
YOLO_VAL 0 32 'hDEADBEEF What else could be in this register??

1.2.1.1.24 DEBUG_REGISTER

   Description: Register for reading out state of the controller. This register is only for debugging purposes!

Offset [AUB] Size [bits] Dimension Volatile Access
'h84 32 0 true read-only

Register DEBUG_REGISTER contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
STUFF_COUNT 0 3 0 Actual stuff count modulo 8 as definned in ISO FD protocol. Stuff count is erased in the beginning of the frame and increased by one with each stuff bit until STUFF count field in ISO FD CRC. Then it stays fixed until the beginning of next frame. In non-ISO FD or normal CAN stuff bits are counted until the end of a frame. Note that this field is NOT gray encoded as defined in ISO FD standard. Stuff count is calculated only as long as controller is transceiving on the bus. During the reception this value remains fixed!
DESTUFF_COUNT 3 3 0 Actual de-stuff count modulo 8 as defined in ISO FD protocol. De-Stuff count is erased in the beginning of the frame and increased by one with each de-stuffed bit until STUFF count field in ISO FD CRC. Then it stays fixed until beginning of next frame. In non-ISO FD or normal CAN de-stuff bits are counted until the end of the frame. Note that this field is NOT grey encoded as defined in ISO FD standard. De-stuff count is calculated in both. Transceiver as well as receiver.
PC_ARB 6 1 0 Protocol control State machine is in Arbitration field.
PC_CON 7 1 0 Protocol control State machine is in Control field.
PC_DAT 8 1 0 Protocol control State machine is in Data field.
PC_CRC 9 1 0 Protocol control State machine is in CRC field.
PC_EOF 10 1 0 Protocol control State machine is in End of file field.
PC_OVR 11 1 0 Protocol control State machine is in Overload field.
PC_INT 12 1 0 Protocol control State machine is in Interrupt field.

1.2.1.1.25 TX_COUNTER

   Description: Counter for transmitted frames to enable bus traffic measurement.

Offset [AUB] Size [bits] Dimension Volatile Access
'h80 32 0 true read-write

Register TX_COUNTER contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TX_COUNTER_VAL 0 32 0 Counter for transcieved frames to enable bus traffic measurement.

1.2.1.1.26 RX_COUNTER

   Description: Counter for received frames to enable bus traffic measurement

Offset [AUB] Size [bits] Dimension Volatile Access
'h7C 32 0 true read-write

Register RX_COUNTER contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RX_COUNTER_VAL 0 32 0 Counter for received frames to enable bus traffic measurement

1.2.1.1.27 ERR_CAPT

   Description: Last error frame capture.

Offset [AUB] Size [bits] Dimension Volatile Access
'h74 8 0 true read-only

Register ERR_CAPT contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
ERR_POS 0 5 'h1F Position of the last error.
ERR_TYPE 5 3 0 Type of the last error

1.2.1.1.28 TX_STATUS

   Description: Status of TXT Buffers.

Offset [AUB] Size [bits] Dimension Volatile Access
'h68 16 0 true read-only

Register TX_STATUS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TX2S 4 4 'h8 Status of TXT Buffer 2. Bit field meaning is analogous to TX1S.
TX1S 0 4 'h8 Status of TXT Buffer 1.
TX3S 8 4 'h8 Status of TXT Buffer 3. Bit field meaning is analogous to TX1S.
TX4S 12 4 'h8 Status of TXT Buffer 4. Bit field meaning is analogous to TX1S.

1.2.1.1.29 TRV_DELAY

Offset [AUB] Size [bits] Dimension Volatile Access
'h78 16 0 true read-only

Register TRV_DELAY contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TRV_DELAY_VALUE 0 16 0 When sending CAN FD Frame with bit rate shift, transceiver delay is measured to apply secondary sampling point for bit error detection during transmission. After the measurement is done (after EDL bit) it can be read from this register. The value in this register is valid since first transmission of CAN FD frame with bit rate shift. After each next measurement the value is updated. This register can be used for transceiver TXD to RXD delay verifcation.

1.2.1.1.30 RX_DATA

Offset [AUB] Size [bits] Dimension Volatile Access
'h64 32 0 true read-only

Register RX_DATA contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RX_DATA 0 32 0 The recieve buffer data at read pointer position in FIFO. CAN Frame layout in RX buffer is described in Figure 7. By reading data from this register read_pointer is automatically increased, as long as there is next data word stored in the buffer. Next Read from this register returns next word of CAN frame. First stored word in the buffer is FRAME_FORM, next TIMESTAMP_U etc. In detail bits of each word have following meaning. If any access is executed (8 bit, 16 bit or 32 bit), the read_pointer automatically increases. It is recomended to use 32 bit acccess on this register.

1.2.1.1.31 RX_POINTERS

   Description: Pointers in the RX FIFO buffer for read (by SW) and write (by Protocol control FSM).

Offset [AUB] Size [bits] Dimension Volatile Access
'h5C 32 0 true read-only

Register RX_POINTERS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RX_WPP 0 12 0 Write pointer position in Receive buffer. During store of received frame write pointer is updated.
RX_RPP 16 12 0 Read pointer position in Receive buffer. During read of received frame read pointer is updated.

1.2.1.1.32 RX_MEM_INFO

   Description: Information register about FIFO memory of RX Buffer.

Offset [AUB] Size [bits] Dimension Volatile Access
'h58 32 0 true read-only

Register RX_MEM_INFO contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RX_BUFF_SIZE 0 13 Size of th Receive buffer. This parameter is configurable before synthesis.
RX_MEM_FREE 16 13 Number of free 32 bit words in the RX Buffer.

1.2.1.1.33 RX_STATUS

   Description: Information register one about FIFO Receive buffer.

Offset [AUB] Size [bits] Dimension Volatile Access
'h60 16 0 true read-only

Register RX_STATUS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RX_EMPTY 0 1 1 Receive buffer is empty.
RX_FULL 1 1 1 Receive buffer is full.
RX_FRC 4 11 0 Receive buffer frame count value.

1.2.1.1.34 FILTER_CONTROL

   Description: Every filter can be configured to accept only selected frame types. Every bit is active in logic 1.

Offset [AUB] Size [bits] Dimension Volatile Access
'h54 16 0 true read-write

Register FILTER_CONTROL contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
FANB 0 1 1 CAN Basic Frame should be accepted by filter A.
FAFB 2 1 1 CAN FD Basic Frame should be accepted by filter A.
FANE 1 1 1 CAN Extended Frame should be accepted by Filter A.
FAFE 3 1 1 CAN FD Extended Frame should be accepted by filter A.
FBNB 4 1 0 CAN Basic Frame should be accepted by filter B.
FBNE 5 1 0 CAN Extended Frame should be accepted by Filter B.
FBFB 6 1 0 CAN FD Basic Frame should be accepted by filter B.
FBFE 7 1 0 CAN FD Extended Frame should be accepted by filter B.
FCNB 8 1 0 CAN Basic Frame should be accepted by filter C.
FCNE 9 1 0 CAN Extended Frame should be accepted by Filter C.
FCFB 10 1 0 CAN FD Basic Frame should be accepted by filter C.
FRFE 15 1 0 CAN FD Extended Frame should be accepted by Range filter.
FRFB 14 1 0 CAN FD Basic Frame should be accepted by Range filter.
FRNE 13 1 0 CAN Extended Frame should be accepted by Range filter.
FRNB 12 1 0 CAN Basic Frame should be accepted by Range filter.
FCFE 11 1 0 CAN FD Extended Frame should be accepted by filter C.

1.2.1.1.35 FILTER_RAN_HIGH

   Description: High Identifier threshold for range filter. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_range=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h50 32 0 true read-write

Register FILTER_RAN_HIGH contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_RAN_HIGH_VAL 0 29 0 High threshold value

1.2.1.1.36 FILTER_RAN_LOW

   Description: Low Identifier threshold for range filter. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_range=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4C 32 0 true read-write

Register FILTER_RAN_LOW contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_RAN_LOW_VAL 0 29 0 Low threshold value

1.2.1.1.37 FILTER_C_VAL

   Description: Bit value for acceptance filter C. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtC=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h48 32 0 true read-write

Register FILTER_C_VAL contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_VAL_C_VAL 0 29 0 Bit Value for acceptance filters to be compared with income identifier. Only bits set in according to FILTER_C_MASK register are compared.

1.2.1.1.38 FILTER_C_MASK

   Description: Bit mask for acceptance filter C. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtC=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h44 32 0 true read-write

Register FILTER_C_MASK contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_MASK_C_VAL 0 29 0 Bit mask for acceptance filters. Logic 1 indicates this bit of Income identifier is compared with the same bit in FILTER_C_VALUE. Logic 0 indicates this bit is not compared.

1.2.1.1.39 FILTER_B_VAL

   Description: Bit value for acceptance filter B. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtB=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h40 32 0 true read-write

Register FILTER_B_VAL contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_VAL_B_VAL 0 29 0 Bit Value for acceptance filters to be compared with income identifier. Only bits set in according to FILTER_B_MASK register are compared.

1.2.1.1.40 FILTER_B_MASK

   Description: Bit mask for acceptance filter B. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtB=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h3C 32 0 true read-write

Register FILTER_B_MASK contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_MASK_B_VAL 0 29 0 Bit mask for acceptance filters. Logic 1 indicates this bit of Income identifier is compared with the same bit in FILTER_B_VALUE. Logic 0 indicates this bit is not compared.

1.2.1.1.41 FILTER_A_MASK

   Description: Bit mask for acceptance filter A. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtA=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes.

Offset [AUB] Size [bits] Dimension Volatile Access
'h34 32 0 true read-write

Register FILTER_A_MASK contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
BIT_MASK_A_VAL 0 29 0 Bit mask for acceptance filters. Logic 1 indicates this bit of Income identifier is compared with the same bit in FILTER_A_VALUE. Logic 0 indicates this bit is not compared.

1.2.1.1.42 CTR_PRES

   Description: Register for manipulation with error counters.

Offset [AUB] Size [bits] Dimension Volatile Access
'h30 32 0 true write-only

Register CTR_PRES contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
CTPV 0 9 0 Counter value to set.
PTX 9 1 0 Preset value from CTR_PRES_VAL to TX Error counter.
PRX 10 1 0 Preset value fromCTR_PRES_VAL to RX Error counter.
ENORM 11 1 0 Erase Nominal bit time error counter.
EFD 12 1 0 Erase Data bit time error counter.

1.2.1.1.43 ERR_FD

Offset [AUB] Size [bits] Dimension Volatile Access
'h2E 16 0 true read-only

Register ERR_FD contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
ERR_FD_VAL 0 16 0 Number of errors in the Data bit time.

1.2.1.1.44 ERR_NORM

Offset [AUB] Size [bits] Dimension Volatile Access
'h2C 16 0 true read-only

Register ERR_NORM contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
ERR_NORM_VAL 0 16 0 Number of errors in the Nominal bit time.

1.2.1.1.45 TXC

   Description: Counter for transcieved frames to enable bus traffic measurement.

Offset [AUB] Size [bits] Dimension Volatile Access
'h2A 16 0 true read-only

Register TXC contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXC_VAL 0 16 0 Counter for transcieved frames to enable bus traffic measurement.

1.2.1.1.46 RXC

   Description: Counter for received frames to enable bus traffic measurement.

Offset [AUB] Size [bits] Dimension Volatile Access
'h28 16 0 true read-only

Register RXC contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
RXC_VAL 0 16 read-only 0 Receive error counter. This register determines Fault confiment state (Error active, Error passive, Bus off) according to CAN specification.

1.2.1.2 TX_Buffer_1

   Description: Access to this memory region is mapped to TXT Buffer 1. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB1_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB1_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB1_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access.

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
memory 'h100 256 32 true

1.2.1.2.1 TXTB1_DATA_1

   Description: This adress word corresponds to FRAME_FORM word

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 32 0

Register TXTB1_DATA_1 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB1_DATA_1 0 32

1.2.1.2.2 TXTB1_DATA_2

   Description: This adress word corresponds to IDENTIFIER word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 32 0

Register TXTB1_DATA_2 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB1_DATA_2 0 32

1.2.1.2.3 TXTB1_DATA_20

   Description: This adress word corresponds to DATA_61_64 word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4C 32 0

Register TXTB1_DATA_20 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB1_DATA_20 0 32

1.2.1.3 TX_Buffer_2

   Description: Access to this memory region is mapped to TXT Buffer 2. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB2_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB2_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB2_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access.

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
memory 'h200 256 32 true

1.2.1.3.1 TXTB2_DATA_1

   Description: This adress word corresponds to FRAME_FORM word

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 32 0

Register TXTB2_DATA_1 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB2_DATA_1 0 32

1.2.1.3.2 TXTB2_DATA_2

   Description: This adress word corresponds to IDENTIFIER word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 32 0

Register TXTB2_DATA_2 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB2_DATA_2 0 32

1.2.1.3.3 TXTB2_DATA_20

   Description: This adress word corresponds to DATA_61_64 word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4C 32 0

Register TXTB2_DATA_20 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB2_DATA_20 0 32

1.2.1.4 TX_Buffer_3

   Description: Access to this memory region is mapped to TXT Buffer 3. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB3_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB3_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB2_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access.

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
memory 'h300 256 32 true

1.2.1.4.1 TXTB3_DATA_1

   Description: This adress word corresponds to FRAME_FORM word

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 32 0

Register TXTB3_DATA_1 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB3_DATA_1 0 32

1.2.1.4.2 TXTB3_DATA_2

   Description: This adress word corresponds to IDENTIFIER word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 32 0

Register TXTB3_DATA_2 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB3_DATA_2 0 32

1.2.1.4.3 TXTB3_DATA_20

   Description: This adress word corresponds to DATA_61_64 word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4C 32 0

Register TXTB3_DATA_20 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB3_DATA_20 0 32

1.2.1.5 TX_Buffer_4

   Description: Access to this memory region is mapped to TXT Buffer 4. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB4_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB4_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB4_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access.

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
memory 'h400 256 32 true

1.2.1.5.1 TXTB4_DATA_1

   Description: This adress word corresponds to FRAME_FORM word

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 32 0

Register TXTB4_DATA_1 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB4_DATA_1 0 32

1.2.1.5.2 TXTB4_DATA_2

   Description: This adress word corresponds to IDENTIFIER word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 32 0

Register TXTB4_DATA_2 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB4_DATA_2 0 32

1.2.1.5.3 TXTB4_DATA_20

   Description: This adress word corresponds to DATA_61_64 word.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4C 32 0

Register TXTB4_DATA_20 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TXTB4_DATA_20 0 32

1.2.1.6 Event_Logger

   Description: Registers for control of Event logger and memory access to event logger RAM. Accessible only when event logger is synthesized.

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
register 'h500 256 32 true

1.2.1.6.1 LOG_TRIG_CONFIG

   Description: Register for configuration of event logging triggering conditions. If Event logger is in Ready state and any of triggering conditions appear it starts recording the events on the bus (moves to Running state). Logic 1 in each bit means this triggering condition is valid.

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 32 0

Register LOG_TRIG_CONFIG contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
T_SOF 0 1 0 Trigger on Start of frame field appears
T_ARBL 1 1 0 Trigger on arbitration was lost
T_REV 2 1 0 Trigger on valid frame received
T_TRV 3 1 0 Trigger on valid frame transmitted.
T_OVL 4 1 0 Trigger when Overload frame is transmitted
T_RES 17 1 0 Trigger when the unit starts receiving a new frame
T_ERR 5 1 0 Trigger on error appeared
T_BRS 6 1 0 Trigger when bit rate is shifted
T_USRW 7 1 0 When logic 1 is written into this bit event logging is triggered immediately
T_ARBS 8 1 0 Trigger on Arbitration field starts
T_CTRS 9 1 0 Trigger on Control field starts
T_ACKNR 13 1 0 Trigger on acknowledge not received in ACK slot
T_EWLR 14 1 0 Trigger on Error warning limit reached
T_ERPC 15 1 0 Trigger on Fault confinement state changed
T_DATS 10 1 0 Trigger on Data field starts
T_ACKR 12 1 0 Trigger on acknowledge received in ACK slot
T_TRS 16 1 0 Trigger when the unit starts transmitting a new frame.
T_CRCS 11 1 0 Trigger on CRC field starts

1.2.1.6.2 LOG_CAPT_CONFIG

   Description: Register for configuring which events to capture by event logger into the logger FIFO memory when event logger is running.

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 32 0

Register LOG_CAPT_CONFIG contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
C_SOF 0 1 0 Capture when Start of frame field appears.
C_ARBL 1 1 0 Capture when arbitration was lost.
C_REV 2 1 0 Capture when valid frame received.
C_TRV 3 1 0 Capture when valid frame transmitted.
C_OVL 4 1 0 Capture when overload appeared.
C_ERR 5 1 0 Capture when error appeared.
C_BRS 6 1 0 Capture when bit rate is shifted.
C_ARBS 7 1 0 Capture when Arbitration field is started.
C_SYNE 17 1 0 Capture when synchronization edge was detected (recessive to dominant edge).
C_STUFF 18 1 0 Capture when Stuff bit was inserted (transceiver only, one fixed stuf bit before CRC sequence is not captured)
C_CTRS 8 1 0 Capture when Control field starts.
C_DESTUFF 19 1 0 Capture when received bit is de-stuffed (receiver and transceiver, one fixed stuff bit before CRC sequence is not captured).
C_DATS 9 1 0 Capture when Data field starts.
C_TRS 15 1 0 Capture when the unit starts transmitting
C_RES 16 1 0 Capture when receive of frame started.
C_OVR 20 1 0 Capture data overrun
C_CRCS 10 1 0 Capture when CRC field starts.
C_ACKR 11 1 0 Capture when Acknowledge was received in ACK Slot.
C_ACKNR 12 1 0 Capture when Acknowledge was not received in ACK Slot.
C_EWLR 13 1 0 Capture when Error warning limit is reached.
C_ERC 14 1 0 Capture when Fault confinement state is changed.

1.2.1.6.3 LOG_STATUS

   Description: Status register for Event logger.

Offset [AUB] Size [bits] Dimension Volatile Access
'h8 16 0

Register LOG_STATUS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
LOG_CFG 0 1 1 Event logger is in Config state
LOG_RDY 1 1 0 Event logger is in Ready state
LOG_RUN 2 1 0 Event logger is in Running state
LOG_EXIST 7 1 Information whether event logger is synthesized in the circuit.
LOG_SIZE 8 8 Size of event logger. This information is valid only if logger is synthesized! (generic "use_logger")

1.2.1.6.4 LOG_POINTERS

   Description: Pointers to Logger RAM memory.

Offset [AUB] Size [bits] Dimension Volatile Access
'hA 16 0

Register LOG_POINTERS contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
LOG_WPP 0 8 0 Write pointer from Event Logging FSM.
LOG_RPP 8 8 0 Read pointer for user access.

1.2.1.6.5 LOG_COMMAND

   Description: Register for controlling the state machine of Event logger and read pointer position. Every bit is active in logic 1.

Offset [AUB] Size [bits] Dimension Volatile Access
'hC 8 0

Register LOG_COMMAND contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
LOG_STR 0 1 0 Start event logging. Move from Config State to Ready state. Has no effect in Ready state or Running state.
LOG_ABT 1 1 0 Abort event logging. Move from Ready State or Running State to Config State.
LOG_UP 2 1 0 Move read pointer one position up.
LOG_DOWN 3 1 0 Move read pointer one position down.

1.2.1.6.6 LOG_CAPT_EVENT_2

   Description: Second word of the captured event at read pointer position.

Offset [AUB] Size [bits] Dimension Volatile Access
'h14 32 0

Register LOG_CAPT_EVENT_2 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
EVNT_TYPE 0 5 0 Type of captured event.
EVNT_DEN 5 3 0 Numerical details of given event. This field captures states of stuffing or destuffing counters when type of recorded event is STF_EVNT or DSTF_EVNT.
EVNT_DET 8 5 0 Details of recorded event. Event details depend on type of the event in EVNT_TYPE.
EVNT_DEA 13 3 0 Additional details of recorded event.
EVENT_TS_15_0 16 16 0 Lowest 16 bits of timestamp at the time when event occured.

1.2.1.6.7 LOG_CAPT_EVENT_1

   Description: First word of the captured event at read pointer position.

Offset [AUB] Size [bits] Dimension Volatile Access
'h10 32 0

Register LOG_CAPT_EVENT_1 contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
EVENT_TS_48_16 0 32 0 Bits 48 to 16 of timestamp at the time when the event occured.

1.2.2 Frame_format

   Description: CAN Frame format describtion in as it is stored in TXT Buffers and RX Buffer.
   Address unit bits (AUB): 8

1.2.2.1 CAN_FD_Frame_format

Usage Base address [AUB] Range [AUB] Width [AUB] Access Volatile
'h0 80 32

1.2.2.1.1 FRAME_FORM_W

   Description: Frame format word with CAN frame metadata.

Offset [AUB] Size [bits] Dimension Volatile Access
'h0 32 0

Register FRAME_FORM_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
DLC 0 4 Data length code as defined in CAN FD Specification.
RTR 5 1 Remote transmission request flag. Has meaning only for CAN frames. CAN FD does not have RTR frames.
ID_TYPE 6 1 Identifier type. Distinguishes between Base and Extended Identifiers.
FR_TYPE 7 1 Frame type. Distinguishes between CAN and CAN FD Frames.
TBF 8 1 Time base format. Should be always set to 1.
BRS 9 1 Bit rate shift. In case of CAN FD frames indicates whether Bit-rate should be shifted during Data phase. This bit has no meaning for CAN Frames.
ESI_RESVD 10 1 Error state indicator bit for received CAN FD frames. Bit has no meaning for CAN frames nor for transmitted CAN FD frames.
RWCNT 11 5 Size of the CAN frame in RX Buffer without FRAME_FORMAT WORD.(E.g RTR frame RWCNT=3, 64 Byte FD frame RWCNT=19). In TXT Buffer this field has no meaning.

1.2.2.1.2 IDENTIFIER_W

   Description: CAN Identifier

Offset [AUB] Size [bits] Dimension Volatile Access
'h4 32 0

Register IDENTIFIER_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
IDENTIFIER_BASE 18 11 Base Identifier of CAN frame
IDENTIFIER_EXT 0 18 Extended Identifier of CAN frame. Has meaning only if ID_TYPE of FRAME_FORMAT_W is EXTENDED.

1.2.2.1.3 TIMESTAMP_L_W

Offset [AUB] Size [bits] Dimension Volatile Access
'h8 32 0

Register TIMESTAMP_L_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TIME_STAMP_31_0 0 32 Lower 32 bits of timestamp when the frame should be transmitted or when it was received.

1.2.2.1.4 TIMESTAMP_U_W

Offset [AUB] Size [bits] Dimension Volatile Access
'hC 32 0

Register TIMESTAMP_U_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
TIMESTAMP_L_W 0 32 Upper 32 bits of timestamp when the frame should be transmitted or when it was received.

1.2.2.1.5 DATA_1_4_W

Offset [AUB] Size [bits] Dimension Volatile Access
'h10 32 0

Register DATA_1_4_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
DATA_1 24 8 Data byte 1 of the CAN Frame.
DATA_2 16 8 Data byte 2 of the CAN Frame.
DATA_3 8 8 Data byte 3 of the CAN Frame.
DATA_4 0 8 Data byte 4 of the CAN Frame.

1.2.2.1.6 DATA_61_64_W

Offset [AUB] Size [bits] Dimension Volatile Access
'h4C 32 0

Register DATA_61_64_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
DATA_61 24 8 Data byte 61 of the CAN Frame.
DATA_62 16 8 Data byte 62 of the CAN Frame.
DATA_63 8 8 Data byte 63 of the CAN Frame.
DATA_64 0 8 Data byte 64 of the CAN Frame.

1.2.2.1.7 DATA_5_8_W

Offset [AUB] Size [bits] Dimension Volatile Access
'h14 32 0

Register DATA_5_8_W contains the following fields:

Field name Offset [bits] Width [bits] Volatile Access Reset value Reset mask Description
DATA_5 24 8 Data byte 5 of the CAN Frame.
DATA_6 16 8 Data byte 6 of the CAN Frame.
DATA_7 8 8 Data byte 7 of the CAN Frame.
DATA_8 0 8 Data byte 8 of the CAN Frame.

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