Generate VHDL registers from IP-XACT
In actual state (8.2.2018) the VHDL package file is generated by pyXact, C header file is generated by pyXact and Lx documentation.
The aim of this task is to create an extension of pyXact and additionally generate VHDL structure which will include all registers (maybe two structures, one for read, one for write direction). The process for memory access to these structures must be generated and instantiated as a sub-module in the can-fd registers.
Such a module would on one side need a memory bus, on the other side, two register structures (one for written and second for read data).
Generated memory access processes would also generate reset values. It would use the same generated address and bitfield constants as it is using now!
The instance of this module would then connect to Driving bus, Status bus and other signals which are driven from/to the registers.
The actual question is how to deal with the side-effects which set the signals at the moment. These are following:
- Interrupt_vector_erase -> This wont be a problem by that time since interrupt vector erase by read will be replaced.
- Generic support such as "sup_filtB", I dont know any way how to set this dependency in IP-XACT.
- RX_buff_read_first -> How should we read data from the RX FIFO then?? I assume this will be a problem, since we cant afford to create a next register for moving to the next word by user write. This would create additional delay on the data read!
Logically the next step after this task would be to replace the Driving Bus and status bus in the whole design by these two structures and use attributes of these structures instead of local aliases. This would allow to drop the index documentation and it would simplify the design, since delection of an element from the registers would immediately reflect to missing element in the structure and thus problem in compilation of any file which would need it!