Feature test clock tolerance
At the moment, both nodes of CTU CAN FD in Feature test environment are feeded with the same clock tolerance:
clk_gen_proc: clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0, out_clk => p(i).clk_sys);
This is not very good, since both nodes will be totally synchronous, and thus errors due to possible malfunction of resynchronisation might not be caught. At this point of design two CTU CAN FD should fully work with asynchronous clocks (as in Sanity test).
This should be fixed and e.g. second node should have clock tolerance of 100 ppm. Even more beneficical would be to calculate maximal clock tolerance from CTU CAN FD standard for Bit Timing settings of Feature test.