CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2018-02-07T18:19:06Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/79Erase the 32 bit register map2018-02-07T18:19:06ZIlle, Ondrej, Ing.Erase the 32 bit register mapTo make the access truly single source, one version of the register map must be erased from the IP-XACT.To make the access truly single source, one version of the register map must be erased from the IP-XACT.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/708 bit register replacement2018-02-06T15:47:21ZIlle, Ondrej, Ing.8 bit register replacementSince the actual implementation of registers is 32 bit there is set of dummy addresses defined in the IP-XACT.
This duplicity is not very good, and was used only temporarily not to have too many changes at the same time!
VHDL package fo...Since the actual implementation of registers is 32 bit there is set of dummy addresses defined in the IP-XACT.
This duplicity is not very good, and was used only temporarily not to have too many changes at the same time!
VHDL package for register map should be re-generated with address offsets from 8 bit register map, the registers
module implementation should be updated and test framework should be modified accordingly.
The advantage of the legacy approach resulted in C header generator which is able to group registers into
bitfield structures of 8,16,32 bits. Thus the update can be done only in HW while the SW header file generator
must only replace the address lookup mechanism with name concatenation of original registers.Single source approachIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/61Prepare the actual documentation for transfer to the register map generation2018-02-06T18:52:25ZIlle, Ondrej, Ing.Prepare the actual documentation for transfer to the register map generationThe actual format of the register map documentation can not be generated
from IP-XACT without loss of information in the docu.
Move all the tables, pictures which are not going to be generated by the
script from IP-XACT into a separate ...The actual format of the register map documentation can not be generated
from IP-XACT without loss of information in the docu.
Move all the tables, pictures which are not going to be generated by the
script from IP-XACT into a separate chapters!
This includes:
RX Data format value into separate chapter describing frame format which will be generated from CAN_FD_frame_format register map
of IP-XACT.
TX Data format
RX Buffer memory layout picture.
Logger register values for EVENT_TYPE.Single source approachIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/57Literal replacement2018-01-24T18:39:09ZIlle, Ondrej, Ing.Literal replacementResearch the source codes of the CAN Core and CAN Test framework
and find places where literals are used. Replace the literals
with constants defined in CANconstants.vhd or another stand-alone
library.Research the source codes of the CAN Core and CAN Test framework
and find places where literals are used. Replace the literals
with constants defined in CANconstants.vhd or another stand-alone
library.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/53Register map documentation2018-02-06T22:03:11ZIlle, Ondrej, Ing.Register map documentationKaktus2 can generate HTML documentation from register maps.
Either replace the register map in Lyx documentation with HTML reference,
or extend the tool from https://github.com/olofk/ipyxact
with Generation of Lyx Chapter which will cont...Kaktus2 can generate HTML documentation from register maps.
Either replace the register map in Lyx documentation with HTML reference,
or extend the tool from https://github.com/olofk/ipyxact
with Generation of Lyx Chapter which will contain the same chapter
structure as actual Register map chapter.Single source approachIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/52C header for driver generation2018-01-27T22:05:24ZIlle, Ondrej, Ing.C header for driver generationExtend the IP XACTL tool from https://github.com/olofk/ipyxact
with generation of header file for Socket CAN driver.
Header file should contain unions for register describtion,
access macros, structures for CAN frame description (either...Extend the IP XACTL tool from https://github.com/olofk/ipyxact
with generation of header file for Socket CAN driver.
Header file should contain unions for register describtion,
access macros, structures for CAN frame description (either custom or overtaken from SocketCAN).Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/51VHDL registers generation2018-01-23T13:38:46ZIlle, Ondrej, Ing.VHDL registers generationExtend the pyxactl tool from https://github.com/olofk/ipyxact
with generation of VHDL constants for CAN FD register map constants.
This includes bit meanings as well as register addresses.Extend the pyxactl tool from https://github.com/olofk/ipyxact
with generation of VHDL constants for CAN FD register map constants.
This includes bit meanings as well as register addresses.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/50IP XACTL for register map2018-01-23T13:38:18ZIlle, Ondrej, Ing.IP XACTL for register mapGenerate IP-XACTL XML file for register map from Cactus 2 software.Generate IP-XACTL XML file for register map from Cactus 2 software.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/49Kaktus2 register map2018-01-23T13:38:35ZIlle, Ondrej, Ing.Kaktus2 register mapCreate project in Kaktus2 software and describe the register map of CAN FD IP Core in its actual version
in this software.Create project in Kaktus2 software and describe the register map of CAN FD IP Core in its actual version
in this software.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/38RX and TX Data register restructuring2017-12-19T16:23:30ZIlle, Ondrej, Ing.RX and TX Data register restructuringCreate two distinct memory locations in the register map which would have RX_DATA and TX_DATA which will be bit aligned.
This will reduce decoder resources.
Update documentation
Update Can test library to be compatible with new register mapCreate two distinct memory locations in the register map which would have RX_DATA and TX_DATA which will be bit aligned.
This will reduce decoder resources.
Update documentation
Update Can test library to be compatible with new register mapFPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/34RX Buffer optimization2017-12-19T16:28:46ZIlle, Ondrej, Ing.RX Buffer optimizationActual implemenetation of RX Buffer decodes the length of the incoming frame twice. Once into "data_length" variable
and once into "data_size" signal. It is desirable that only one decoder will be used.Actual implemenetation of RX Buffer decodes the length of the incoming frame twice. Once into "data_length" variable
and once into "data_size" signal. It is desirable that only one decoder will be used.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/33Add status bits2017-12-28T10:57:42ZIlle, Ondrej, Ing.Add status bitsNew optimizations involved adding pre-synthesis generics such as : filter support and tx_time support.
It is necessary to add status bit indicating support of these features to the SW.New optimizations involved adding pre-synthesis generics such as : filter support and tx_time support.
It is necessary to add status bit indicating support of these features to the SW.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/17Identifier optimization2017-12-09T17:36:58ZIlle, Ondrej, Ing.Identifier optimizationUnify the identifier transmission in Protocol control.
Use shift register instead of direct addressing of the identifier.Unify the identifier transmission in Protocol control.
Use shift register instead of direct addressing of the identifier.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/16RX CRC optimization2017-12-09T14:27:58ZIlle, Ondrej, Ing.RX CRC optimizationRemove the direct addressing by shift-register on received CRC.Remove the direct addressing by shift-register on received CRC.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/15Bus sync optimization2018-01-02T23:00:16ZIlle, Ondrej, Ing.Bus sync optimizationssp_shift shift register for secondary sampling point of the Data phase during FD transmission is problematic from resource usage
point of view.
Think of solutions for this. Can we remove direct addressing?? I assume not, since the leng...ssp_shift shift register for secondary sampling point of the Data phase during FD transmission is problematic from resource usage
point of view.
Think of solutions for this. Can we remove direct addressing?? I assume not, since the length of the shift register
is not fixed (it is given by transceiver delay)...FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/14CAN CRC optimization2017-12-09T14:25:40ZIlle, Ondrej, Ing.CAN CRC optimizationAdd optimization for addressing of CAN CRC inside the Protocol control counter.
The idea is to load the CRC at the beginning of the CRC phase and use shift-register
during the transmission instead of direct adressing in the crc15,crc17,c...Add optimization for addressing of CAN CRC inside the Protocol control counter.
The idea is to load the CRC at the beginning of the CRC phase and use shift-register
during the transmission instead of direct adressing in the crc15,crc17,crc21 signals.
This should save some logic inside the protocol control!FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/11Configurable filter support2017-12-05T12:12:36ZIlle, Ondrej, Ing.Configurable filter supportAdd configurable filter support. Thus it can be decided before synthesis if this filter will be supported.
Each filter needs identifier value and identifier mask 2*29 Flip-flops . Thus e.g. if only one identifier should be captured by a...Add configurable filter support. Thus it can be decided before synthesis if this filter will be supported.
Each filter needs identifier value and identifier mask 2*29 Flip-flops . Thus e.g. if only one identifier should be captured by any unit,
then it does not have sense to have support of all filters!FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/7TX buffer into SRAM2017-12-05T12:12:17ZIlle, Ondrej, Ing.TX buffer into SRAMThe actual implementation of the TXT buffer is using Flip-flops. In order to use SRAM memory on FPGA, the load of the data into the CAN core must be serialized, since FPGAs does not offer 640-bit width memories. This task involves creati...The actual implementation of the TXT buffer is using Flip-flops. In order to use SRAM memory on FPGA, the load of the data into the CAN core must be serialized, since FPGAs does not offer 640-bit width memories. This task involves creation of the FSM for serial loading the TX frame into CAN Core. This task must be implemented after the serialization of access from user registers and after adding the frame droppig feature and must be compliant with both of these features. As first, identifier must be loaded to the CAN Core, beacuse loading will také up to 20 clock cycles. If the identifier is not already stored in the CAN Core during the first bit of the Identifier transmission, Invalid value will be transmitted. This situation must be avoided.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/5Change of RX data read from RX buffer2017-12-19T16:28:55ZIlle, Ondrej, Ing.Change of RX data read from RX bufferThis modification involves changing architecture of the RX FIFO buffer. The RX FIFO buffer has actually parallel data interface from the IP Core (whole CAN frame is available in parallel). Once the frame is properly received (EOF field),...This modification involves changing architecture of the RX FIFO buffer. The RX FIFO buffer has actually parallel data interface from the IP Core (whole CAN frame is available in parallel). Once the frame is properly received (EOF field), the signal „rec_valid“ starts loading the frame into the RX buffer. The frame is stored in following up to 20 clock cycles, 32-bit word per clock cycle. The other part of the RX Buffer has only one 32-bit word at a time available. This word corresponds to address of the „read_pointer“ value. „read_pointer“ is incremented by each read on Avalon Interface. Read of the frame is performed by repetitive read from the same address.
The aim of this modification is to create the same interface between RX Buffer and registers (Avalon) as between RX Buffer and CAN Core. This involves modifying the register map of the IP Core. Offset on the Avalon bus will be added to the read pointer and it will create direct address to the RAM memory of RX Buffer. Avalon Adress must be added combinationally to the read pointer value, to be able to get the data on the output of the RAM in the next clock cycle. The multiplexor must be created to drive the RAM address based on the Avalon address range. Actual implementation moves to the next word in the memory (increments read pointer) by performing the Avalon read. Additional bit must be added to register map. Writing logic 1 into this bit will increment the value of the pointer to point to the first word of next CAN frame. Thus user would be responsible for erasing the frame from RX buffer after reading it!
An optional inference of the RX Buffer via VHDL generic must be added during this step. This option will allow to either inferr or not inferr the RX buffer. In the case of the buffer presence the Avalon address will create the RAM address based on chosen register. In the absence of the RX buffer the Avalon address would create the offset in the parallel interface on the ouput of CAN Core. In case of Buffer absence the user is responsible for reading the frame soon enough before the Core erases it at the SOF of next frame!FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/3Sync/Async reset2017-11-30T15:24:56ZIlle, Ondrej, Ing.Sync/Async resetAdd proper reset synchronisation.Add proper reset synchronisation.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.