CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2018-04-05T10:48:23Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/80Socket CAN driver low level draft2018-04-05T10:48:23ZIlle, Ondrej, Ing.Socket CAN driver low level draftEither extend the original driver or create a new one for Socket CAN with usage of native Linux structures. Create additional header file include which could be used by Mr. Novak for his project where Linux structures are not present!Either extend the original driver or create a new one for Socket CAN with usage of native Linux structures. Create additional header file include which could be used by Mr. Novak for his project where Linux structures are not present!Socket CAN release features2018-03-15https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/77Finalize the Socket CAN driver header format2018-03-26T14:12:02ZIlle, Ondrej, Ing.Finalize the Socket CAN driver header formatCreate the final version of the socket CAN driver header.Create the final version of the socket CAN driver header.Socket CAN release features2018-03-15https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/466Test improvements2023-12-17T21:15:57ZIlle, Ondrej, Ing.Test improvementsCoverage analysis towards v2.5 has shown several places where additional tests would be good.
Several were written, others are pending.
Following test would be good to be written / extended:
1. [ ] Extend `retr_limit`, `retr_limit_2` an...Coverage analysis towards v2.5 has shown several places where additional tests would be good.
Several were written, others are pending.
Following test would be good to be written / extended:
1. [ ] Extend `retr_limit`, `retr_limit_2` and `retr_limit_3` to iterate over all available TXT Buffers.
2. [ ] Extend `tst_mem_acc_rx` to write the memory also via March pattern, not only random data pattern. This will give us full toggle coverage on all bits on RX Buffer even if 4096 width is tested.
3. [ ] Attempt to cover simultaneous events in RX Buffer in main TB. RX Buffer is intensively verified by its unit test. This unit test contains a model of RX Buffer, and hits these cases. RX Buffer unit test needs to be re-added to CI run (currently not there after porting to VCS flow) with GHDL. Despite having the concurent comit/read and abort/read covered by RX Buffer unit test, it would be good to cover these situations also in main TB, since code coverage is generated from main TB. Since VCS nor NVC can generate coverage from completely different designs (coverage is hierarchy based), it would be good to hit these cases also in main TB.
4. [ ] Check if GHDL already supports External names. If yes, then generalize the VCS hack for random data deposit in few tests.
5. [ ] Write test that covers "transient state" to Failed transition in case of Bus-off. Iterate over all TXT Buffers.
6. [ ] Write test that covers saturation of SSP delay condition.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/465Optimizations for better coverage2023-12-19T15:48:27ZIlle, Ondrej, Ing.Optimizations for better coverageThe coverage analysis executed with VCS during verification towards v2.5 revealed potential
design optimizations to reduce number of unreachable coverage bins in various blocks.
This is a tracking issue to work on these.
The main point...The coverage analysis executed with VCS during verification towards v2.5 revealed potential
design optimizations to reduce number of unreachable coverage bins in various blocks.
This is a tracking issue to work on these.
The main point is to optimize the code in a way where too generic design patterns cause
lot of unreachable code to be generated. This leads to requirement for tedious exclude files
if high coverage numbers are needed.
Following design patterns causing unreachable design were identified:
1. [ ] Reduce width of counters in Prescaler based on value they can count up-to the most.
This affects, segment counter, prescaler, extension, etc... See from v2.5 exclude file.
2. [ ] Split Protocol control FSM into two FSMs: Protocol control and Error transmission.
Error transmission FSM would handle Error Active/Passive Flag transmission, as well as
moving to "integration" state upon Error condition in ROM mode. A Protocol control FSM
would have a single state, that would indicate that the control over the transmission
is passed to Error transmission FSM. Once error transmission FSM would be over doing
its job, it would signal back to Protocol Control FSM. This would drastically reduce
number of available FSM transitions in FSM coverage.
3. [ ] Rework "Access signaller" in generated register map. Current approach is waaay to
generic. Split the access signaller to "Read" and "Write"
4. [ ] Rework Data MUX in the generated register map. Current approach, where all read data
are concatenated to one large vector and padded by zeroes, causes that there is way
too many toggles that are constant driven. It is very tedious to do the coverage analysis then.
Also, VCS with SX license does not provide the option to automatically exclude constant
driven items. So, it would be better to generate non-generic data mux module that would
have all register values brought in as ports, and the register selection would be done
inside of the generated data mux. Padding by zeroes then could be done in the process
that would mux the registers to "data_out" signal. This would get rid of many uncoverable
toggles.
5. [x] Rework the way that Protocol control FSM gives signals to TXT Buffers. Currently,
`txtb_hw_cmd` has `unlock` that is active together with either of `failed`, `error` or `arbl`.
Due to the design of next state decoder in protocol control FSM, and encoding of `txtb_hw_cmd`,
there are unreachable expressions and branches in the TXT Buffer FSM.
6. [ ] Split Odd and Even TXT Buffer implementation into a separate files. Even
TXT Buffers can never be Backup Buffers, and thus they can never be skipped during TXT Buffer
Backup mode operation. Thus there is lot of unreachable logic that needed to be waived.
7. [x] Make only MSB of init vector configurable via port in `crc_calc`.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/464xilinx ise-14.7 reports of Gated clock - build is attempt to setup NuttX dri...2023-10-19T18:51:50ZPavel Pisaxilinx ise-14.7 reports of Gated clock - build is attempt to setup NuttX driver development on LX_CPU (LPC4088 + XC6SLX9)The Xst reports
```
WARNING:PhysDesignRules:372 - Gated clock. Clock net
can_fd_instances_for[0].can_fd_inst/bus_sampling_inst/bit_err_detector_inst/r
es_n_inv is sourced by a combinatorial pin. This is not good design practice.
...The Xst reports
```
WARNING:PhysDesignRules:372 - Gated clock. Clock net
can_fd_instances_for[0].can_fd_inst/bus_sampling_inst/bit_err_detector_inst/r
es_n_inv is sourced by a combinatorial pin. This is not good design practice.
Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
can_fd_instances_for[0].can_fd_inst/can_core_inst/fault_confinement_inst/faul
t_confinement_fsm_inst/fc_fsm_res_q_inv is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
```
More investigation of troubles found on this old tool-chain is ongoing.
Project build with minimal configuration successfully, frames are sent but acknowledge from other side is weak, works when XCAN is used but when another CTU CAN FD or CAN to USB converter are used then transmission fails. Reception is not successful too.
Setup has chance to easily test CTU CAN FD with NuttX and have environment for NuttX driver development because PiKRON's LX_CPU support is included in NuttX mainline.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/463G_TECHNOLOGY/target_technology generic is not documented in CTU CAN FD Core ...2023-12-15T13:38:54ZPavel PisaG_TECHNOLOGY/target_technology generic is not documented in CTU CAN FD Core Datasheet nor System Architecture DocumentationIt can be chosen from C_TECH_FPGA or C_TECH_ASIC and default is target_technology := C_TECH_FPGA in can_top_level, can_top_ahb and can_top_apb so it should be correct for use in FPGAs. But datasheet should document all generics.It can be chosen from C_TECH_FPGA or C_TECH_ASIC and default is target_technology := C_TECH_FPGA in can_top_level, can_top_ahb and can_top_apb so it should be correct for use in FPGAs. But datasheet should document all generics.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/462Flip to VCS flow2023-12-15T16:18:49ZIlle, Ondrej, Ing.Flip to VCS flowhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/460driver: update to build with old and 6.5+ kernel version2023-09-06T13:13:34ZPavel Pisadriver: update to build with old and 6.5+ kernel versionApply minor changes and adjustments from mainline Linux kernel driver to allow standalone build with old and new kernel versions. The ifdefs not acceptable into mainline are required to allow build with older and new kernels from the sin...Apply minor changes and adjustments from mainline Linux kernel driver to allow standalone build with old and new kernel versions. The ifdefs not acceptable into mainline are required to allow build with older and new kernels from the single sources.
Code update is done on the old IP core version the first to check compatibility with all versions which are supported by mainline sources.Pavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/459Debug remaning compliance tests2023-02-19T09:40:08ZIlle, Ondrej, Ing.Debug remaning compliance testshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/458SYN warnings2023-02-19T19:38:49ZIlle, Ondrej, Ing.SYN warnings```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/tx_arbitrator/priority_decoder.vhd:199: Initial values for signals/variables are not supported for synthesis by default. They are ignored. (VHD-7)
Warning: /home/oille/Downloads/c...```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/tx_arbitrator/priority_decoder.vhd:199: Initial values for signals/variables are not supported for synthesis by default. They are ignored. (VHD-7)
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/tx_arbitrator/priority_decoder.vhd:243: Initial values for signals/variables are not supported for synthesis by default. They are ignored. (VHD-7)
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/tx_arbitrator/priority_decoder.vhd:204: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/tx_arbitrator/priority_decoder.vhd:249: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
```
```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/memory_registers/generated/address_decoder.vhd:139: Attribute 'IMAGE is not supported for synthesis and will be ignored. (ELAB-936)
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/memory_registers/generated/address_decoder.vhd:139: Attribute 'IMAGE is not supported for synthesis and will be ignored. (ELAB-936)
```
```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/memory_registers/generated/address_decoder.vhd:139: Attribute 'IMAGE is not supported for synthesis and will be ignored. (ELAB-936)
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/memory_registers/generated/address_decoder.vhd:139: Attribute 'IMAGE is not supported for synthesis and will be ignored. (ELAB-936)
```
```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/can_core/err_detector.vhd:296: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
```
```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/can_core/tx_shift_reg.vhd:257: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
```
```
Warning: /home/oille/Downloads/ctucanfd_ip_core/src/rx_buffer/rx_buffer.vhd:548: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
```https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/457Update CI job tags2023-01-21T19:49:42ZIlle, Ondrej, Ing.Update CI job tagshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/456Docs mention removed release creation script2023-09-28T12:04:42ZEmil Jiří TywoniakDocs mention removed release creation scriptIn doc/core/ctu_can_fd_architecture.lyx line 1441 "RTL release can be created by following script:" and onward references scripts/create_release.py removed in 10b5a64e8cd4e7fb2f0b67200459ed489fa50be7. `gitlab-runner exec shell pages` is ...In doc/core/ctu_can_fd_architecture.lyx line 1441 "RTL release can be created by following script:" and onward references scripts/create_release.py removed in 10b5a64e8cd4e7fb2f0b67200459ed489fa50be7. `gitlab-runner exec shell pages` is sadly not a replacement as it fails on `cp: cannot stat 'test/rtl_lst.txt': No such file or directory` which needs to be created earlier in the pipeline, and `gitlab-runner` doesn't seem to support running a pipeline or multiple stages locally. Unfortunately, the user should be probably informed to download the release from gitlab instead.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/455Add test for disabled parity detection2022-09-05T21:19:40ZIlle, Ondrej, Ing.Add test for disabled parity detectionhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/454Flip to manually launched regression on master, not every day run2022-08-03T12:38:16ZIlle, Ondrej, Ing.Flip to manually launched regression on master, not every day runhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/453Flip to OSVVM from VUnit2023-03-12T09:54:29ZIlle, Ondrej, Ing.Flip to OSVVM from VUnithttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/452Add NVC run scripts2023-12-17T20:43:17ZIlle, Ondrej, Ing.Add NVC run scriptsCurrently, NVC compiler is able to compile whole CTU CAN FD,
including TB.
VUnit does not support NVC, but NVC can be manually used by means
of hand-written makefile.
At the moment NVC does not support PSL assertions, so the whole
regr...Currently, NVC compiler is able to compile whole CTU CAN FD,
including TB.
VUnit does not support NVC, but NVC can be manually used by means
of hand-written makefile.
At the moment NVC does not support PSL assertions, so the whole
regression will not switch to NVC yet, but it might be good to
run at least small regression in NVC (feature tests only, since
compliance library is written with GHDL specific VPI).https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/451Add loopback flag to frame in RX Buffer2023-12-19T15:50:21ZIlle, Ondrej, Ing.Add loopback flag to frame in RX BufferCurrently time of transmission can be added to TXT Buffer, but during high bus load
this does not mean that frame will be actually transmitted at this time.
In case of loop-back mode, it would be desirable to known when the frame was ac...Currently time of transmission can be added to TXT Buffer, but during high bus load
this does not mean that frame will be actually transmitted at this time.
In case of loop-back mode, it would be desirable to known when the frame was actually transmitted.
To distinguish loopback frames from regularly received frames, it would be good to add
"Loopback flag" per received frame in RX Buffer.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/450Add integration guide document2023-12-17T20:35:13ZIlle, Ondrej, Ing.Add integration guide documentCurrently,
there are already two users who were confused about connection of `timestamp` input to all 0xFF
if there is no timestamp in their system. This information is present in System architecture
document, but it is not easy to fin...Currently,
there are already two users who were confused about connection of `timestamp` input to all 0xFF
if there is no timestamp in their system. This information is present in System architecture
document, but it is not easy to find.
It would be good to create separate "Integration" guide document.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/449Integrate compliance library as sub-module2022-07-23T19:25:33ZIlle, Ondrej, Ing.Integrate compliance library as sub-modulehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/448Clean-up all Vivado synthesis warnings2022-07-18T20:34:42ZIlle, Ondrej, Ing.Clean-up all Vivado synthesis warnings