...
 
Commits (1)
......@@ -96,20 +96,23 @@ entity CTU_CAN_FD_v1_0 is
s_apb_pslverr : out std_logic;
s_apb_pstrb : in std_logic_vector(3 downto 0);
s_apb_pwdata : in std_logic_vector(31 downto 0);
s_apb_pwrite : in std_logic
s_apb_pwrite : in std_logic;
drv_bus_o : out std_logic_vector(1023 downto 0);
stat_bus_o : out std_logic_vector(511 downto 0)
);
end entity CTU_CAN_FD_v1_0;
architecture rtl of CTU_CAN_FD_v1_0 is
signal reg_data_in : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal reg_addr : std_logic_vector(23 downto 0);
signal reg_be : std_logic_vector(3 downto 0);
signal reg_rden : std_logic;
signal reg_wren : std_logic;
signal drv_bus : std_logic_vector(1023 downto 0);
signal stat_bus : std_logic_vector(511 downto 0);
begin
i_can : CAN_top_level
generic map (
use_logger => use_logger,
......@@ -139,8 +142,13 @@ begin
CAN_rx => CAN_rx,
time_quanta_clk => time_quanta_clk,
timestamp => timestamp
timestamp => timestamp,
drv_bus_o => drv_bus,
stat_bus_o => stat_bus
);
drv_bus_o <= drv_bus;
stat_bus_o <= stat_bus;
i_apb : apb_ifc
port map (
......
......@@ -323,6 +323,40 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>drv_bus_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1023</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>stat_bus_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">511</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>s_apb_paddr</spirit:name>
<spirit:wire>
......
......@@ -95,10 +95,8 @@ package can_components is
signal CAN_tx : out std_logic;
signal CAN_rx : in std_logic;
signal time_quanta_clk : out std_logic;
-- synthesis translate_off
signal drv_bus_o : out std_logic_vector(1023 downto 0);
signal stat_bus_o : out std_logic_vector(511 downto 0);
-- synthesis translate_on
signal timestamp : in std_logic_vector(63 downto 0)
);
end component;
......