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Commits (73)
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################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
##
## Script for generation of Lyx table headers from VHDL entities interface.
## Recognizes generics and ports. Recognizes comments before signals.
## Splits signals into sections. Each section is started by "large" comment
## which is delimited by whole line of comment characters like so:
##
## --------------------------------------------------------------------------
## -- My fancy section of signals which I would like to have in docs!
## --------------------------------------------------------------------------
## -- This signal is so cool!
## device_is_completely_stuck : in std_logic;
##
## -- Restart the whole device
## restart_q : out std_logic;
##
###############################################################################
##
## Arguments:
## configPath Path to YAML config file which specifies files that will
## be generated.
##
## Revision history:
## 22.03.2019 Implemented the script
##
################################################################################
import argparse
import sys
import time
import importlib.util
import os
import inspect
import math
import yaml
import pyXact_generator
from pyXact_generator.gen_lib import *
from pyXact_generator.VhdlLyxEntityGeneratorWrapper import VhdlLyxEntityGeneratorWrapper
def parse_args():
parser = argparse.ArgumentParser(
description="""Script for generation of Lyx Tables from VHDL
entity interfaces""")
parser.add_argument('--configPath', dest='configPath', help="""Path to YAML
config file""")
return parser.parse_args();
if __name__ == '__main__':
args = parse_args()
print( 80 * "*")
print("** Generating Lyx docs for VHDL entity interfaces!")
print(80 * "*")
pythonVersion = sys.version.split('.')
pythonCmd = "python" + pythonVersion[0] + "." + pythonVersion[1]
print("\n Python version is: %s \n" % pythonCmd)
with open(args.configPath, 'rt') as f:
config = yaml.safe_load(f)
gen = VhdlLyxEntityGeneratorWrapper()
gen.set_config(config)
gen.do_update()
print( 80 * "*")
print("** Finished")
print(80 * "*")
Subproject commit 4e78535d62f76ae5a0b91819ab6cbb914cba4662
Subproject commit 210cc07c4b2b9948bafbec6e2b03b0257c70e8de
template: "../doc/core/template.lyx"
source_list:
can_core:
vhdl_file: "../src/can_core/can_core.vhd"
lyx_output: "../doc/core/entity_docs/can_core.lyx"
......@@ -55,7 +55,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -64,7 +63,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -79,6 +77,9 @@ entity apb_ifc is
aclk : in std_logic;
arstn : in std_logic;
-----------------------------------------------------------------------
-- CTU CAN FD Interface
-----------------------------------------------------------------------
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
......@@ -86,6 +87,9 @@ entity apb_ifc is
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
-----------------------------------------------------------------------
-- APB interface
-----------------------------------------------------------------------
s_apb_paddr : in std_logic_vector(31 downto 0);
s_apb_penable : in std_logic;
s_apb_pprot : in std_logic_vector(2 downto 0);
......
......@@ -49,7 +49,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -58,7 +57,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -67,55 +65,53 @@ use work.CAN_FD_frame_format.all;
entity bit_error_detector is
generic(
-- Reset polarity
constant reset_polarity : std_logic
G_RESET_POLARITY : std_logic
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- System clock
clk_sys :in std_logic;
-- Asynchronous reset
res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Bit error detection enabled
signal bit_err_enable :in std_logic;
-- Core is enabled
signal drv_ena :in std_logic;
-- CTU CAN FD Core is enabled
drv_ena :in std_logic;
-- Sample control (nominal, data, secondary)
signal sp_control :in std_logic_vector(1 downto 0);
-- Sample control
sp_control :in std_logic_vector(1 downto 0);
-- Input sample signals
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
-- RX Trigger
rx_trigger :in std_logic;
-- RX Trigger - Secondary Sample
sample_sec :in std_logic;
-----------------------------------------------------------------------
-- TX Data inputs
-- TX / RX Datapath
-----------------------------------------------------------------------
-- Regulary transmitted data
signal data_tx :in std_logic;
-- Actually transmitted data on CAN bus
data_tx :in std_logic;
-- Delayed transmitted data (for detection in secondary sampling point)
signal data_tx_delayed :in std_logic;
data_tx_delayed :in std_logic;
-----------------------------------------------------------------------
-- RX Data inputs
-----------------------------------------------------------------------
-- Receieved data in Nominal Bit time (either directly sampled data,
-- or tripple sampling output)
signal data_rx_nbt :in std_logic;
-- Receieved data in Nominal Bit time
data_rx_nbt :in std_logic;
-- Received data (Nominal and Data)
signal can_rx_i :in std_logic;
-- Received data (both Nominal Bit time and Data Bit time)
can_rx_i :in std_logic;
------------------------------------------------------------------------
-- Bit error output
------------------------------------------------------------------------
signal bit_error : out std_logic
-----------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------
-- Bit error detected
bit_error : out std_logic
);
end entity;
......@@ -139,10 +135,8 @@ begin
----------------------------------------------------------------------------
-- Sample point multiplexor
----------------------------------------------------------------------------
sample <= sample_nbt when (sp_control = NOMINAL_SAMPLE) else
sample_dbt when (sp_control = DATA_SAMPLE) else
sample_sec when (sp_control = SECONDARY_SAMPLE) else
'0';
sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else
rx_trigger;
----------------------------------------------------------------------------
-- Expected data mux. Choose between TX data and delayed TX Data
......@@ -160,7 +154,7 @@ begin
-- Bit Error detection. If expected data is not equal to actual data in
-- sample point -> Bit Error!
----------------------------------------------------------------------------
bit_error_d <= '0' when (drv_ena = CTU_CAN_DISABLED or bit_err_enable = '0') else
bit_error_d <= '0' when (drv_ena = CTU_CAN_DISABLED) else
'1' when (exp_data /= act_data and sample = '1') else
'0' when (exp_data = act_data and sample = '1') else
bit_error_q;
......@@ -170,7 +164,7 @@ begin
----------------------------------------------------------------------------
bit_error_reg_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
bit_error_q <= '0';
elsif (rising_edge(clk_sys)) then
bit_error_q <= bit_error_d;
......
This diff is collapsed.
......@@ -67,7 +67,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -76,7 +75,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -85,42 +83,39 @@ use work.CAN_FD_frame_format.all;
entity data_edge_detector is
generic(
-- Reset polarity
constant reset_polarity : std_logic;
-- Pipeline TX edge output (insert DFF)
constant tx_edge_pipeline : boolean := true;
-- Pipeline RX edge output (insert DFF)
constant rx_edge_pipeline : boolean := true
G_RESET_POLARITY : std_logic
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
-- Clock and Asynchronous reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- System clock
clk_sys :in std_logic;
-- Asynchronous Reset
res_n :in std_logic;
------------------------------------------------------------------------
-- Inputs
------------------------------------------------------------------------
-- TX Data from CAN Core
signal tx_data :in std_logic;
tx_data :in std_logic;
-- RX Data (synced from CAN Bus)
signal rx_data :in std_logic;
-- RX Data (from CAN Bus)
rx_data :in std_logic;
-- RX Data value sampled in previous Sample point.
signal prev_rx_sample :in std_logic;
-- RX Data value from previous Sample point.
prev_rx_sample :in std_logic;
------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------
-- Edge detected on TX
signal tx_edge :out std_logic;
-- Edge detected on TX Data
tx_edge :out std_logic;
-- Edge detected on RX
signal rx_edge :out std_logic
);
-- Edge detected on RX Data
rx_edge :out std_logic
);
end entity;
......@@ -134,10 +129,6 @@ architecture rtl of data_edge_detector is
signal rx_edge_immediate : std_logic;
signal tx_edge_immediate : std_logic;
-- Valid edge
signal rx_edge_valid : std_logic;
signal tx_edge_valid : std_logic;
-- Internal value of output signals
signal rx_edge_i : std_logic;
signal tx_edge_i : std_logic;
......@@ -150,7 +141,7 @@ begin
----------------------------------------------------------------------------
data_reg_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
rx_data_prev <= RECESSIVE;
tx_data_prev <= RECESSIVE;
elsif (rising_edge(clk_sys)) then
......@@ -176,10 +167,10 @@ begin
-- 1. Edge on tx_data
-- 2. RECESSIVE to DOMINANT
----------------------------------------------------------------------------
tx_edge_valid <= '1' when (tx_edge_immediate = '1') and
(tx_data_prev = RECESSIVE)
else
'0';
tx_edge_i <= '1' when (tx_edge_immediate = '1') and
(tx_data_prev = RECESSIVE)
else
'0';
----------------------------------------------------------------------------
-- Valid RX Edge:
......@@ -188,51 +179,16 @@ begin
-- 3. Data sampled in previous Sample point are different from actual
-- rx_data immediately after edge.
----------------------------------------------------------------------------
rx_edge_valid <= '1' when (rx_edge_immediate = '1') and
(rx_data_prev = RECESSIVE) and
(prev_rx_sample /= rx_data)
else
'0';
rx_edge_i <= '1' when (rx_edge_immediate = '1') and
(rx_data_prev = RECESSIVE) and
(prev_rx_sample /= rx_data)
else
'0';
----------------------------------------------------------------------------
-- Driving rx_edge output
-- Internal signals to output propagation
----------------------------------------------------------------------------
rx_edge_pipeline_gen_true : if (rx_edge_pipeline) generate
rx_edge_pipeline_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
rx_edge_i <= '0';
elsif (rising_edge(clk_sys)) then
rx_edge_i <= rx_edge_valid;
end if;
end process;
end generate rx_edge_pipeline_gen_true;
rx_edge_pipeline_gen_false : if (not rx_edge_pipeline) generate
rx_edge_i <= rx_edge_valid;
end generate rx_edge_pipeline_gen_false;
rx_edge <= rx_edge_i;
----------------------------------------------------------------------------
-- Driving tx_edge output
----------------------------------------------------------------------------
tx_edge_pipeline_gen_true : if (tx_edge_pipeline) generate
tx_edge_pipeline_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
tx_edge_i <= '0';
elsif (rising_edge(clk_sys)) then
tx_edge_i <= tx_edge_valid;
end if;
end process;
end generate tx_edge_pipeline_gen_true;
tx_edge_pipeline_gen_false : if (not tx_edge_pipeline) generate
tx_edge_i <= tx_edge_valid;
end generate tx_edge_pipeline_gen_false;
tx_edge <= tx_edge_i;
end architecture;
end architecture;
\ No newline at end of file
......@@ -49,7 +49,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -58,7 +57,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -67,51 +65,48 @@ use work.CAN_FD_frame_format.all;
entity sample_mux is
generic(
-- Reset polarity
constant reset_polarity : std_logic;
-- Pipeline data output
constant pipeline_sampled_data : boolean := true
G_RESET_POLARITY : std_logic := '0'
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- System clock
clk_sys :in std_logic;
-- Asynchronous reset
res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- CTU CAN FD enabled
signal drv_ena :in std_logic;
drv_ena :in std_logic;
-- Sample control (nominal, data, secondary)
signal sp_control :in std_logic_vector(1 downto 0);
sp_control :in std_logic_vector(1 downto 0);
-- Input sample signals
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
-- RX Trigger
rx_trigger :in std_logic;
-- RX Trigger - Secondary Sampling
sample_sec :in std_logic;
-----------------------------------------------------------------------
-- RX Data inputs
-- Datapath
-----------------------------------------------------------------------
-- Receieved data in Nominal Bit time (either directly sampled data,
-- or tripple sampling output)
signal data_rx_nbt :in std_logic;
-- Receieved data in Nominal Bit time
data_rx_nbt :in std_logic;
-- Received data (Nominal and Data)
signal can_rx_i :in std_logic;
-- Received data (Nominal Bit Time and Data Bit Time)
can_rx_i :in std_logic;
------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------
-- Sampled value of RX in Sample point (DFF output)
signal prev_sample : out std_logic;
-- Sampled value of RX pin in Sample point (DFF output)
prev_sample :out std_logic;
-- Sampled value of RX in Sample point (either DFF or direct output)
signal data_rx : out std_logic
);
-- Sampled value of RX pin in Sample point (either DFF or direct output)
data_rx :out std_logic
);
end entity;
architecture rtl of sample_mux is
......@@ -131,10 +126,8 @@ begin
----------------------------------------------------------------------------
-- Sample point multiplexor
----------------------------------------------------------------------------
sample <= sample_nbt when (sp_control = NOMINAL_SAMPLE) else
sample_dbt when (sp_control = DATA_SAMPLE) else
sample_sec when (sp_control = SECONDARY_SAMPLE) else
'0';
sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else
rx_trigger;
----------------------------------------------------------------------------
-- RX data mux.
......@@ -150,7 +143,7 @@ begin
sample_prev_req_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
sample_prev_q <= RECESSIVE;
elsif (rising_edge(clk_sys)) then
if (drv_ena = '1') then
......@@ -160,16 +153,9 @@ begin
end process;
----------------------------------------------------------------------------
-- Receive data. If pipeline is inserted, then use directly sample_prev,
-- if not, then pipe the input to output directly!
-- Internal signal to output propagation
----------------------------------------------------------------------------
insert_pipeline_true_gen : if (pipeline_sampled_data = true) generate
data_rx <= sample_prev_q;
end generate insert_pipeline_true_gen;
insert_pipeline_false_gen : if (pipeline_sampled_data = false) generate
data_rx <= rx_data_i;
end generate insert_pipeline_false_gen;
rx_data_i <= rx_data_i;
-- Internal signal to output propagation
prev_sample <= sample_prev_q;
......
......@@ -101,7 +101,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -110,7 +109,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -119,88 +117,91 @@ use work.CAN_FD_frame_format.all;
entity trv_delay_measurement is
generic(
-- Reset polarity
constant reset_polarity : std_logic;
G_RESET_POLARITY : std_logic;
-- Width (number of bits) in transceiver delay measurement counter
constant trv_ctr_width : natural := 7;
G_TRV_CTR_WIDTH : natural := 7;
-- Optional usage of saturated value of ssp_delay
constant use_ssp_saturation : boolean := true;
G_USE_SSP_SATURATION : boolean := true;
-- Saturation level for size of SSP_delay. This is to make sure that
-- if there is smaller shift register for secondary sampling point we
-- don't address outside of this register.
constant ssp_saturation_lvl : natural
G_SSP_SATURATION_LVL : natural
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
-- Clock and Asynchronous reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- System clock
clk_sys :in std_logic;
-- Asynchronous reset
res_n :in std_logic;
------------------------------------------------------------------------
-- Measurement control
-- Transceiver Delay measurement control
------------------------------------------------------------------------
signal meas_start :in std_logic;
signal meas_stop :in std_logic;
signal meas_enable :in std_logic;
-- Start measurement (on TX Edge)
meas_start :in std_logic;
-- Stop measurement (on RX Edge)
meas_stop :in std_logic;
-- Measurement enabled (by Protocol control)
meas_enable :in std_logic;
------------------------------------------------------------------------
-- Control registers interface
-- Memory registers interface
------------------------------------------------------------------------
signal ssp_offset :in std_logic_vector(
trv_ctr_width - 1 downto 0);
signal ssp_delay_select :in std_logic_vector(1 downto 0);
-- Secondary sampling point offset
ssp_offset :in std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
-- Source of secondary sampling point
-- (Measured, Offset, Measured and Offset)
ssp_delay_select :in std_logic_vector(1 downto 0);
------------------------------------------------------------------------
-- Status outputs
------------------------------------------------------------------------
-- Transceiver delay measurement is in progress
signal trv_meas_progress :out std_logic;
trv_meas_progress :out std_logic;
-- Shadowed value of trv_delay.
signal trv_delay_shadowed :out std_logic_vector(
trv_ctr_width - 1 downto 0);
-- Shadowed value of Transceiver delay. Updated when measurement ends.
trv_delay_shadowed :out std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
-- Shadowed value of SSP configuration.
signal ssp_delay_shadowed :out std_logic_vector(
trv_ctr_width downto 0)
);
-- Shadowed value of SSP configuration. Updated when measurement ends.
ssp_delay_shadowed :out std_logic_vector(G_TRV_CTR_WIDTH downto 0)
);
end entity;
architecture rtl of trv_delay_measurement is
-- Transceiver delay measurement next value
signal trv_meas_progress_nxt : std_logic;
signal trv_meas_progress_nxt : std_logic;
-- Transceiver delay measurement - internal register value
signal trv_meas_progress_i : std_logic;
signal trv_meas_progress_i : std_logic;
-- Delayed value of trv_meas_progress to detect when measurement has ended
-- and load ssp_offset shadow register.
signal trv_meas_progress_del : std_logic;
signal trv_meas_progress_del : std_logic;
---------------------------------------------------------------------------
-- Transceiver delay counter
---------------------------------------------------------------------------
signal trv_delay_ctr_reg : std_logic_vector(
trv_ctr_width - 1 downto 0);
signal trv_delay_ctr_rst : std_logic;
signal trv_delay_ctr_add : std_logic_vector(
trv_ctr_width - 1 downto 0);
signal trv_delay_ctr_reg : std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
signal trv_delay_ctr_rst : std_logic;
signal trv_delay_ctr_add : std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
---------------------------------------------------------------------------
-- SSP Shadowed register
---------------------------------------------------------------------------
signal ssp_shadowed_nxt : std_logic;
signal ssp_shadowed_nxt : std_logic;
-- Load shadow register to output
signal ssp_shadow_load : std_logic;
signal ssp_shadow_load : std_logic;
---------------------------------------------------------------------------
-- Shadowed value of transceiver delay counter
......@@ -208,18 +209,14 @@ architecture rtl of trv_delay_measurement is
-- Note that output counter is one bit wider than width of counter since
-- output value can be addition of two values of trv_ctr_width size and
-- we want to avoid overflow.
signal ssp_delay_nxt : std_logic_vector(
trv_ctr_width downto 0);
signal ssp_delay_nxt : std_logic_vector(G_TRV_CTR_WIDTH downto 0);
-- Saturated value of ssp_delay. If saturation is not used, ssp_delay_nxt
-- is connected directly
signal ssp_delay_saturated : std_logic_vector(
trv_ctr_width downto 0);
signal ssp_delay_saturated : std_logic_vector(G_TRV_CTR_WIDTH downto 0);
-- Measured transceiver value + trv_offset
signal trv_delay_sum : std_logic_vector(
trv_ctr_width downto 0);
signal trv_delay_sum : std_logic_vector(G_TRV_CTR_WIDTH downto 0);
begin
......@@ -240,7 +237,7 @@ begin
----------------------------------------------------------------------------
trv_delay_prog_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
trv_meas_progress_i <= '0';
trv_meas_progress_del <= '0';
elsif (rising_edge(clk_sys)) then
......@@ -267,7 +264,7 @@ begin
----------------------------------------------------------------------------
trv_del_ctr_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity or trv_delay_ctr_rst = '1') then
if (res_n = G_RESET_POLARITY or trv_delay_ctr_rst = '1') then
trv_delay_ctr_reg <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
......@@ -311,12 +308,12 @@ begin
ssp_delay_nxt_int <= to_integer(unsigned(ssp_delay_nxt));
-- Use saturation
ssp_sat_true : if (use_ssp_saturation) generate
ssp_sat_true : if (G_USE_SSP_SATURATION) generate
-- Saturate on "natural" types
ssp_delay_sat_int <=
ssp_saturation_lvl when (ssp_delay_nxt_int > ssp_saturation_lvl)
else
G_SSP_SATURATION_LVL when (ssp_delay_nxt_int > G_SSP_SATURATION_LVL)
else
ssp_delay_nxt_int;
-- Convert natural back to vector
......@@ -326,7 +323,7 @@ begin
end generate ssp_sat_true;
-- Don't use saturation
ssp_sat_false : if (not use_ssp_saturation) generate
ssp_sat_false : if (not G_USE_SSP_SATURATION) generate
ssp_delay_saturated <= ssp_delay_nxt;
end generate ssp_sat_false;
......@@ -341,7 +338,7 @@ begin
---------------------------------------------------------------------------
ssp_shadow_reg_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
ssp_delay_shadowed <= (OTHERS => '0');
trv_delay_shadowed <= (OTHERS => '0');
......@@ -364,11 +361,9 @@ begin
else
'0';
---------------------------------------------------------------------------
-- Propagation of internal signals to output
---------------------------------------------------------------------------
trv_meas_progress <= trv_meas_progress_i;
end architecture;
end architecture;
\ No newline at end of file
......@@ -51,7 +51,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -60,7 +59,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -69,63 +67,67 @@ use work.CAN_FD_frame_format.all;
entity tx_data_cache is
generic(
-- Reset polarity
constant reset_polarity : std_logic;
G_RESET_POLARITY : std_logic := '0';
-- Depth of FIFO (Number of bits that can be stored)
constant tx_cache_depth : natural range 4 to 32 := 8;
G_TX_CACHE_DEPTH : natural range 4 to 32 := 8;
-- FIFO reset value
constant tx_cache_res_val : std_logic
G_TX_CACHE_RST_VAL : std_logic := '0'
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
-- Clock and Asynchronous reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- System clock
clk_sys :in std_logic;
-- Asynchronous reset
res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Store input data
signal write :in std_logic;
write :in std_logic;
-- Read output data
signal read :in std_logic;
read :in std_logic;
------------------------------------------------------------------------
-- Data signals
------------------------------------------------------------------------
signal data_in :in std_logic;
signal data_out :out std_logic
);
-- Data inputs
data_in :in std_logic;
-- Data output
data_out :out std_logic
);
end entity;
architecture rtl of tx_data_cache is
-- Cache Memory (FIFO in DFFs)
signal tx_cache_mem : std_logic_vector(tx_cache_depth - 1 downto 0);
signal tx_cache_mem : std_logic_vector(G_TX_CACHE_DEPTH - 1 downto 0);
---------------------------------------------------------------------------
-- Access pointers
---------------------------------------------------------------------------
-- Write Pointer
signal write_pointer : natural range 0 to tx_cache_depth - 1;
signal write_pointer_nxt : natural range 0 to tx_cache_depth - 1;
signal write_pointer : natural range 0 to G_TX_CACHE_DEPTH - 1;
signal write_pointer_nxt : natural range 0 to G_TX_CACHE_DEPTH - 1;
-- Read pointer
signal read_pointer : natural range 0 to tx_cache_depth - 1;
signal read_pointer_nxt : natural range 0 to tx_cache_depth - 1;
signal read_pointer : natural range 0 to G_TX_CACHE_DEPTH - 1;
signal read_pointer_nxt : natural range 0 to G_TX_CACHE_DEPTH - 1;
begin
----------------------------------------------------------------------------
-- Combinationally incrementing write and read pointers
----------------------------------------------------------------------------
write_pointer_nxt <= (write_pointer + 1) mod tx_cache_depth;
read_pointer_nxt <= (read_pointer + 1) mod tx_cache_depth;
write_pointer_nxt <= (write_pointer + 1) mod G_TX_CACHE_DEPTH;
read_pointer_nxt <= (read_pointer + 1) mod G_TX_CACHE_DEPTH;
----------------------------------------------------------------------------
......@@ -133,7 +135,7 @@ begin
----------------------------------------------------------------------------
write_ptr_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
write_pointer <= 0;
elsif (rising_edge(clk_sys)) then
if (write = '1') then
......@@ -145,7 +147,7 @@ begin
read_ptr_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
read_pointer <= 0;
elsif (rising_edge(clk_sys)) then
if (read = '1') then
......@@ -160,8 +162,8 @@ begin
----------------------------------------------------------------------------
tx_cache_mem_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
tx_cache_mem <= (OTHERS => tx_cache_res_val);
if (res_n = G_RESET_POLARITY) then
tx_cache_mem <= (OTHERS => G_TX_CACHE_RST_VAL);
elsif (rising_edge(clk_sys)) then
if (write = '1') then
tx_cache_mem(write_pointer) <= data_in;
......@@ -177,62 +179,25 @@ begin
data_out <= tx_cache_mem(read_pointer);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Assertions on input signals
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Monitor overflow of both pointers (as if highest bit), and check that:
-- 1. There is no read when FIFO is empty
-- 2. It never happends that FIFO is full and write occurs, this is
-- failure, since design does not have this control and would corrupt
-- previous data. This is not expected to happend since 8 bits in FIFO
-- means de-facto 8 bits on the fly on CAN Bus. This is crazy and no
-- one will ever use it! Just in case something like this happends be
-- sure that it is caught in simulation...
----------------------------------------------------------------------------
-- pragma translate_off
assert_proc : process
variable write_ptr_higher : boolean := true;
variable cache_full : boolean := false;
variable cache_empty : boolean := false;
begin
wait until rising_edge(clk_sys);
-- Write overflows -> Write is now under read
if (write = '1' and write_pointer = tx_cache_depth - 1) then
write_ptr_higher := false;
end if;
-- Read overflows -> Read is now under write
if (read = '1' and read_pointer = tx_cache_depth - 1) then
write_ptr_higher := true;
end if;
-- Find out if cache is full or empty!
if (read_pointer = write_pointer) then
if (write_ptr_higher) then
cache_full := true;
else
cache_empty := true;
end if;
end if;
-- Check that if FIFO is empty no read occurs
-- if (cache_empty and read = '1') then
-- report "Should not read from empty TX Data cache -> BUG!"
-- severity failure;
-- end if;
-- Check that if FIFO is full no write occurs
-- if (cache_full and read = '1') then
-- report "Should not write to full TX Data cache -> BUG!"
-- severity failure;
-- end if;
end process;
-- pragma translate_on
-- psl default clock is rising_edge(clk_sys);
-- Here be stricter to make the check easier! Allow at least one bit free
-- in the FIFO!
-- psl no_fifo_overflow_asrt : assert never
-- ((read_pointer - 1 = write_pointer) and (write = '1'))
-- report "TX Cache is full, there should be less than 4 bits on the fly!"
-- severity error;
-- psl no_empty_read : assert never
-- (read = '1' and write_pointer = read_pointer)
-- report "Read from empty TX CACHE"
-- severity error;
--
-- Note: When read pointer is equal to write pointer, FIFO is for sure
-- empty, because we detect error when it is almost full. So we never get
-- to situation that read pointer equals write pointer when FIFO is full!
end architecture;
end architecture;
\ No newline at end of file
This diff is collapsed.
......@@ -52,7 +52,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -61,48 +60,65 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity bus_traffic_counters is
generic(
-- Reset polarity
G_RESET_POLARITY : std_logic := '0'
);
port(
------------------------------------------------------------------------
-- System clock and Reset
-- System clock and Asynchronous Reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- Clear signals (used as async. reset, not preload to lower resource
-- usage)
signal clear_rx_ctr :in std_logic;
signal clear_tx_ctr :in std_logic;
-- System clock
clk_sys :in std_logic;
-- Asynchronous Reset
res_n :in std_logic;
-- Increment signals (upon sucesfull transmission or reception of frame)
signal inc_tx_ctr :in std_logic;
signal inc_rx_ctr :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Clear RX Traffic counter (Glitch free)
clear_rx_ctr :in std_logic;
-- Clear TX Traffic counter (Glitch free)
clear_tx_ctr :in std_logic;
-- Increment TX Traffic Counter
inc_tx_ctr :in std_logic;
-- Increment RX Traffic Counter
inc_rx_ctr :in std_logic;
------------------------------------------------------------------------
-- Counter outputs
signal tx_ctr :out std_logic_vector(31 downto 0);
signal rx_ctr :out std_logic_vector(31 downto 0)
------------------------------------------------------------------------
-- TX Traffic counter
tx_ctr :out std_logic_vector(31 downto 0);
-- RX Traffic counter
rx_ctr :out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of bus_traffic_counters is
signal tx_ctr_int : std_logic_vector(31 downto 0);
signal rx_ctr_int : std_logic_vector(31 downto 0);
signal tx_ctr_int : std_logic_vector(31 downto 0);
signal rx_ctr_int : std_logic_vector(31 downto 0);
-- Input selector
signal sel : std_logic;
signal sel : std_logic;
-- Selected value to increment
signal sel_value : std_logic_vector(31 downto 0);
signal sel_value : std_logic_vector(31 downto 0);
-- Incremented value by 1
signal inc_value : std_logic_vector(31 downto 0);
signal inc_value : std_logic_vector(31 downto 0);
begin
......@@ -126,7 +142,7 @@ begin
----------------------------------------------------------------------------
tx_ctr_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET or clear_tx_ctr = '1') then
if (res_n = G_RESET_POLARITY or clear_tx_ctr = '1') then
tx_ctr_int <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
......@@ -142,7 +158,7 @@ begin
----------------------------------------------------------------------------
rx_ctr_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET or clear_rx_ctr = '1') then
if (res_n = G_RESET_POLARITY or clear_rx_ctr = '1') then
rx_ctr_int <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
......@@ -153,11 +169,13 @@ begin
end process;
---------------------------------------------------------------------------
-- Assertion that both inputs are not active at the same time since only
-- single adder is used. This would corrupt counter values.
-- Assertions
---------------------------------------------------------------------------
assert not (inc_tx_ctr = '1' and inc_rx_ctr = '1') report
"RX frame counter and TX frame counter can't be incremented at once"
severity error;
end architecture;
-- psl default clock is rising_edge(clk_sys);
-- psl no_simul_inc_tx_rx_asrt : assert never
-- (inc_tx_ctr = '1' and inc_rx_ctr = '1')
-- report "Simultaneous increment of TX and RX error traffic counter"
-- severity error;
end architecture;
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
......@@ -56,7 +56,6 @@
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
......@@ -65,7 +64,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -73,57 +71,54 @@ use work.CAN_FD_frame_format.all;
entity crc_calc is
generic(
-- Reset polarity
G_RESET_POLARITY : std_logic := '0';
-- Width of CRC sequence
constant crc_width : natural;
-- Reset Polarity
constant reset_polarity : std_logic := '0';
G_CRC_WIDTH : natural;
-- CRC Polynomial
constant polynomial : std_logic_vector
G_POLYNOMIAL : std_logic_vector
);
port(
------------------------------------------------------------------------
-- Inputs
-- System clock and Asynchronous Reset
------------------------------------------------------------------------
-- System clock input
clk_sys :in std_logic;
-- Asynchronous reset
signal res_n :in std_logic;
-- System clock input
signal clk_sys :in std_logic;
res_n :in std_logic;
-- Serial data input
signal data_in :in std_logic;
------------------------------------------------------------------------
-- CRC Calculation control
------------------------------------------------------------------------
-- Serial data input for CRC calculation
data_in :in std_logic;
-- Trigger to sample the input value
signal trig :in std_logic;
-- Trigger to sample the input data
trig :in std_logic;
-- By transition from 0 to 1 on enable sampled on clk_sys rising edge
-- (and with trig='1') operation is started. First bit of data already
-- has to be on data_in input.
-- Circuit works as long as enable=1.
signal enable :in std_logic;
-- CRC calculation enabled
enable :in std_logic;
-- Initialization vector for CRC calculation
signal init_vect :in std_logic_vector(crc_width - 1 downto 0);
init_vect :in std_logic_vector(G_CRC_WIDTH - 1 downto 0);
------------------------------------------------------------------------
-- CRC value
-- CRC output
------------------------------------------------------------------------
signal crc :out std_logic_vector(crc_width - 1 downto 0)
crc :out std_logic_vector(G_CRC_WIDTH - 1 downto 0)
);
end entity;
architecture rtl of crc_calc is
----------------------------------------------------------------------------
-- Internal registers
----------------------------------------------------------------------------
signal crc_reg : std_logic_vector(crc_width - 1 downto 0);
-- CRC register
signal crc_reg : std_logic_vector(G_CRC_WIDTH - 1 downto 0);
-- Holds previous value of enable input. Detects 0 to 1 transition
signal start_reg : std_logic;
......@@ -132,25 +127,24 @@ architecture rtl of crc_calc is
signal crc_nxt : std_logic;
-- Shifted value of CRC register. Insert 0 from left
signal crc_shift : std_logic_vector(crc_width - 1 downto 0);
signal crc_shift : std_logic_vector(G_CRC_WIDTH - 1 downto 0);
-- XORed value
signal crc_shift_n_xor : std_logic_vector(crc_width - 1 downto 0);
signal crc_shift_n_xor : std_logic_vector(G_CRC_WIDTH - 1 downto 0);
-- Combinational value of next CRC value
signal crc_nxt_val : std_logic_vector(crc_width - 1 downto 0);
signal crc_nxt_val : std_logic_vector(G_CRC_WIDTH - 1 downto 0);
begin
----------------------------------------------------------------------------
-- Calculation of next CRC value
----------------------------------------------------------------------------
crc_nxt <= data_in xor crc_reg(crc_width - 1);
crc_nxt <= data_in xor crc_reg(G_CRC_WIDTH - 1);
crc_shift <= crc_reg(crc_width - 2 downto 0) & '0';
crc_shift <= crc_reg(G_CRC_WIDTH - 2 downto 0) & '0';
crc_shift_n_xor <= crc_shift xor polynomial(crc_width - 1 downto 0);
crc_shift_n_xor <= crc_shift xor G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);
crc_nxt_val <= crc_shift_n_xor when (crc_nxt = '1')
else
......@@ -161,7 +155,7 @@ begin
----------------------------------------------------------------------------
start_reg_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
if (res_n = G_RESET_POLARITY) then
start_reg <= '0';
elsif rising_edge(clk_sys) then
start_reg <= enable;
......@@ -173,7 +167,7 @@ begin
----------------------------------------------------------------------------
crc_calc_proc : process(res_n, clk_sys)
begin