...
 
Commits (4)
......@@ -8740,7 +8740,7 @@ cellcolor{cyan}
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
OFI\end_layout
\end_inset
</cell>
......@@ -8821,7 +8821,7 @@ cellcolor{cyan}
\begin_inset Text
\begin_layout Plain Layout
-\end_layout
0\end_layout
\end_inset
</cell>
......@@ -8910,6 +8910,9 @@ ALI Arbitration lost Interrupt. Interrupt set has priority over clear.
BEI Bus Error interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
OFI Overload frame Interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
RXFI Receive Buffer full interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
......@@ -268,7 +268,7 @@ union ctu_can_fd_int_stat {
uint32_t epi : 1;
uint32_t ali : 1;
uint32_t bei : 1;
uint32_t reserved_7 : 1;
uint32_t ofi : 1;
uint32_t rxfi : 1;
uint32_t bsi : 1;
uint32_t rbnei : 1;
......@@ -280,7 +280,7 @@ union ctu_can_fd_int_stat {
uint32_t rbnei : 1;
uint32_t bsi : 1;
uint32_t rxfi : 1;
uint32_t reserved_7 : 1;
uint32_t ofi : 1;
uint32_t bei : 1;
uint32_t ali : 1;
uint32_t epi : 1;
......
......@@ -646,6 +646,18 @@
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
<ipxact:field>
<ipxact:name>OFI</ipxact:name>
<ipxact:description>Overload frame Interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXBHCI</ipxact:name>
<ipxact:displayName>TXBHCI</ipxact:displayName>
......
......@@ -211,6 +211,9 @@ entity can_core is
-- Error warning limit reached
error_warning_limit :out std_logic;
-- Overload frame is being transmitted
is_overload :out std_logic;
------------------------------------------------------------------------
-- Prescaler interface
......@@ -408,7 +411,7 @@ architecture rtl of can_core is
signal is_error : std_logic;
signal is_intermission : std_logic;
signal is_suspend : std_logic;
signal is_overload : std_logic;
signal is_overload_i : std_logic;
signal sof_pulse_i : std_logic;
......@@ -451,7 +454,7 @@ begin
is_intermission => is_intermission, -- OUT
is_suspend => is_suspend, -- OUT
is_error => is_error, -- OUT
is_overload => is_overload, -- OUT
is_overload => is_overload_i, -- OUT
-- TXT Buffers interface
tran_word => tran_word, -- IN
......@@ -815,7 +818,7 @@ begin
-- 2. Looped back dominant Bit for Bus monitoring Mode.
-- 3. Regular RX Data
---------------------------------------------------------------------------
bds_data_in <= bst_data_out when (sp_control = SECONDARY_SAMPLE) else
bds_data_in <= bst_data_out when (sp_control_i = SECONDARY_SAMPLE) else
lpb_dominant when (drv_bus_mon_ena = '1') else
rx_data_wbs;
......@@ -894,7 +897,7 @@ begin
is_error;
stat_bus(STAT_PC_IS_OVERLOAD_INDEX) <=
is_overload;
is_overload_i;
stat_bus(STAT_ARB_LOST_INDEX) <=
arbitration_lost_i;
......@@ -1070,7 +1073,7 @@ begin
error_warning_limit_i;
stat_bus(STAT_ERROR_VALID_INDEX) <=
err_detected;
err_detected_i;
stat_bus(STAT_ACK_RECIEVED_OUT_INDEX) <=
ack_received_i;
......@@ -1112,5 +1115,6 @@ begin
trv_delay_calib <= trv_delay_calib_i;
is_bus_off <= is_bus_off_i;
sof_pulse <= sof_pulse_i;
is_overload <= is_overload_i;
end architecture;
\ No newline at end of file
......@@ -417,6 +417,9 @@ architecture rtl of can_top_level is
-- Bit Rate Was Shifted
signal br_shifted : std_logic;
-- Overload frame is being transmitted
signal is_overload : std_logic;
------------------------------------------------------------------------
-- CAN Core <-> Prescaler Interface
------------------------------------------------------------------------
......@@ -735,6 +738,7 @@ begin
rx_full => rx_full, -- IN
rx_empty => rx_empty, -- IN
txtb_hw_cmd_int => txtb_hw_cmd_int, -- IN
is_overload => is_overload, -- IN
-- Memory registers Interface
drv_bus => drv_bus, -- IN
......@@ -801,6 +805,7 @@ begin
err_detected => err_detected, -- OUT
error_passive_changed => error_passive_changed, -- OUT
error_warning_limit => error_warning_limit, -- OUT
is_overload => is_overload, -- OUT
-- Prescaler interface
rx_triggers => rx_triggers, -- IN
......
......@@ -145,6 +145,9 @@ entity int_manager is
-- HW command on TXT Buffers interrupt
txtb_hw_cmd_int :in std_logic_vector(G_TXT_BUFFER_COUNT - 1 downto 0);
-- Overload frame is being transmitted
is_overload :in std_logic;
------------------------------------------------------------------------
-- Memory registers Interface
......@@ -255,8 +258,8 @@ begin
int_input_active(RBNEI_IND) <= not rx_empty;
int_input_active(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int);
-- Logger finished interrupt removed after logger was thrown out!
int_input_active(7) <= '0';
-- Overload frame interrupt
int_input_active(OFI_IND) <= is_overload;
---------------------------------------------------------------------------
-- Interrupt module instances
......@@ -370,4 +373,11 @@ begin
-- psl txbhci_enable_cov : cover
-- (int_vect_i(TXBHCI_IND) = '1' and int_ena(TXBHCI_IND) = '1');
-- psl ofi_int_set_cov : cover
-- {int_vect_i(OFI_IND) = '0';int_vect_i(OFI_IND) = '1'};
-- psl ofi_enable_cov : cover
-- (int_vect_i(OFI_IND) = '1' and int_ena(OFI_IND) = '1');
end architecture;
\ No newline at end of file
......@@ -1442,6 +1442,7 @@ package can_components is
-- Overload frame is being transmitted
is_overload :out std_logic;
-----------------------------------------------------------------------
-- Data-path interface
-----------------------------------------------------------------------
......@@ -2524,6 +2525,9 @@ package can_components is
-- Error warning limit reached
error_warning_limit :out std_logic;
-- Overload frame is being transmitted
is_overload :out std_logic;
------------------------------------------------------------------------
-- Prescaler interface
......@@ -2761,6 +2765,9 @@ package can_components is
-- HW command on TXT Buffers interrupt
txtb_hw_cmd_int :in std_logic_vector(G_TXT_BUFFER_COUNT - 1 downto 0);
-- Overload frame is being transmitted
is_overload :in std_logic;
------------------------------------------------------------------------
-- Memory registers Interface
......
......@@ -624,6 +624,7 @@ package can_fd_register_map is
constant EPI_IND : natural := 4;
constant ALI_IND : natural := 5;
constant BEI_IND : natural := 6;
constant OFI_IND : natural := 7;
constant RXFI_IND : natural := 8;
constant BSI_IND : natural := 9;
constant RBNEI_IND : natural := 10;
......@@ -640,6 +641,7 @@ package can_fd_register_map is
constant RXFI_RSTVAL : std_logic := '0';
constant BSI_RSTVAL : std_logic := '0';
constant RBNEI_RSTVAL : std_logic := '0';
constant OFI_RSTVAL : std_logic := '0';
constant TXBHCI_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
......
......@@ -182,10 +182,10 @@ begin
int_stat_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111101111111" ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111101111111"
auto_clear => "0000111111111111"
)
port map(
clk_sys => clk_sys ,-- in
......
......@@ -100,6 +100,9 @@ architecture int_man_unit_test of CAN_test is
-- HW command on TX Buffer
signal txtb_hw_cmd_int : std_logic_vector(C_TXT_BUFFER_COUNT - 1 downto 0);
-- Overload frame is being transmitted
signal is_overload : std_logic;
----------------------------------------------
-- Status signals
----------------------------------------------
......@@ -181,8 +184,10 @@ architecture int_man_unit_test of CAN_test is
signal rx_empty :inout std_logic;
-- TXT HW Command
signal txtb_hw_cmd_int :inout std_logic_vector(C_TXT_BUFFER_COUNT - 1
downto 0)
signal txtb_hw_cmd_int :inout std_logic_vector(C_TXT_BUFFER_COUNT - 1
downto 0);
signal is_overload :inout std_logic
)is
variable tmp : std_logic;
begin
......@@ -245,6 +250,12 @@ architecture int_man_unit_test of CAN_test is
else
rand_logic_s(rand_ctr, rx_empty, 0.05);
end if;
if (is_overload = '1') then
rand_logic_s(rand_ctr, is_overload, 0.95);
else
rand_logic_s(rand_ctr, is_overload, 0.05);
end if;
for i in 0 to C_TXT_BUFFER_COUNT - 1 loop
if (txtb_hw_cmd_int(i) = '1') then
......@@ -326,6 +337,7 @@ begin
rx_data_overrun => rx_data_overrun ,
rec_valid => rec_valid ,
rx_full => rx_full,
is_overload => is_overload,
drv_bus => drv_bus ,
int => int,
int_vector => int_vector,
......@@ -344,6 +356,7 @@ begin
int_input(RXFI_IND) <= rx_full;
int_input(BSI_IND) <= br_shifted;
int_input(RBNEI_IND) <= not rx_empty;
int_input(OFI_IND) <= is_overload;
int_input(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int);
......@@ -369,7 +382,7 @@ begin
generate_sources(rand_ctr_1, err_detected, error_passive_changed ,
error_warning_limit , arbitration_lost, tran_valid,
br_shifted, rx_data_overrun , rec_valid ,
rx_full , rx_empty, txtb_hw_cmd_int);
rx_full , rx_empty, txtb_hw_cmd_int, is_overload);
end loop;
end process;
......