...
 
Commits (10)
......@@ -8740,7 +8740,7 @@ cellcolor{cyan}
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
OFI\end_layout
\end_inset
</cell>
......@@ -8821,7 +8821,7 @@ cellcolor{cyan}
\begin_inset Text
\begin_layout Plain Layout
-\end_layout
0\end_layout
\end_inset
</cell>
......@@ -8910,6 +8910,9 @@ ALI Arbitration lost Interrupt. Interrupt set has priority over clear.
BEI Bus Error interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
OFI Overload frame Interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
RXFI Receive Buffer full interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
......@@ -268,7 +268,7 @@ union ctu_can_fd_int_stat {
uint32_t epi : 1;
uint32_t ali : 1;
uint32_t bei : 1;
uint32_t reserved_7 : 1;
uint32_t ofi : 1;
uint32_t rxfi : 1;
uint32_t bsi : 1;
uint32_t rbnei : 1;
......@@ -280,7 +280,7 @@ union ctu_can_fd_int_stat {
uint32_t rbnei : 1;
uint32_t bsi : 1;
uint32_t rxfi : 1;
uint32_t reserved_7 : 1;
uint32_t ofi : 1;
uint32_t bei : 1;
uint32_t ali : 1;
uint32_t epi : 1;
......
......@@ -193,7 +193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>bd93fd12</spirit:value>
<spirit:value>87bf052c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -209,7 +209,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>bd93fd12</spirit:value>
<spirit:value>87bf052c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -223,7 +223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>aabbb6d4</spirit:value>
<spirit:value>0743f567</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -486,11 +486,6 @@
<spirit:displayName>Rx Buffer Size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.rx_buffer_size" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">128</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>use_sync</spirit:name>
<spirit:displayName>Use Sync</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.use_sync">true</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>sup_filtA</spirit:name>
<spirit:displayName>Sup Filta</spirit:displayName>
......@@ -559,28 +554,18 @@
<spirit:file>
<spirit:name>xgui/CTU_CAN_FD_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_aabbb6d4</spirit:userFileType>
<spirit:userFileType>CHECKSUM_0743f567</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>CTU_CAN_FD_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>use_logger</spirit:name>
<spirit:displayName>Use Logger</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.use_logger">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>rx_buffer_size</spirit:name>
<spirit:displayName>Rx Buffer Size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.rx_buffer_size" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">128</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>use_sync</spirit:name>
<spirit:displayName>Use Sync</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.use_sync">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sup_filtA</spirit:name>
<spirit:displayName>Sup Filta</spirit:displayName>
......@@ -601,11 +586,6 @@
<spirit:displayName>Sup Range</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.sup_range">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>logger_size</spirit:name>
<spirit:displayName>Logger Size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.logger_size" spirit:minimum="0" spirit:maximum="512" spirit:rangeType="long">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">CTU_CAN_FD_v1_0</spirit:value>
......@@ -623,20 +603,20 @@
</xilinx:taxonomies>
<xilinx:displayName>CTU_CAN_FD_v1_0</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2019-01-07T11:37:47Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>5</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2019-05-27T16:56:46Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
<xilinx:tag xilinx:name="user.org:user:CTU_CAN_FD:1.0_ARCHIVE_LOCATION">/home/pi/fpga/zynq/canbech-sw/modules/CTU_CAN_FD/src</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
<xilinx:xilinxVersion>2018.2.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="c572df2c"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cdef2cce"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4e435b33"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="0d5541f6"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5d342b85"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="72b5e748"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="cddf56a5"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
Subproject commit 210cc07c4b2b9948bafbec6e2b03b0257c70e8de
Subproject commit aa2bb9d95d64cd48b6d7d3d2c219082b753e34c8
......@@ -646,6 +646,18 @@
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
<ipxact:field>
<ipxact:name>OFI</ipxact:name>
<ipxact:description>Overload frame Interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXBHCI</ipxact:name>
<ipxact:displayName>TXBHCI</ipxact:displayName>
......
......@@ -449,8 +449,7 @@ begin
-- 2. Set to RECESSIVE when non-fixed bit stuffing changes to fixed
-- bit stuffing. TODO: IS THIS OK???
---------------------------------------------------------------------------
prev_val_d <= RECESSIVE when (destuff_enable = '1' and enable_prev = '0') else
RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
data_in when (bds_trigger = '1') else
prev_val_q;
......
......@@ -408,8 +408,7 @@ begin
-- 3. Pipe the input data upon trigger without stufffing
-- 4. Keep previous value otherwise
---------------------------------------------------------------------------
data_out_nxt_ena <= RECESSIVE when (enable_prev = '0') else
(not data_out_int) when (bst_trigger = '1' and insert_stuff_bit = '1') else
data_out_nxt_ena <= (not data_out_int) when (bst_trigger = '1' and insert_stuff_bit = '1') else
data_in when (bst_trigger = '1') else
data_out_int;
......
......@@ -211,6 +211,9 @@ entity can_core is
-- Error warning limit reached
error_warning_limit :out std_logic;
-- Overload frame is being transmitted
is_overload :out std_logic;
------------------------------------------------------------------------
-- Prescaler interface
......@@ -408,7 +411,7 @@ architecture rtl of can_core is
signal is_error : std_logic;
signal is_intermission : std_logic;
signal is_suspend : std_logic;
signal is_overload : std_logic;
signal is_overload_i : std_logic;
signal sof_pulse_i : std_logic;
......@@ -451,7 +454,7 @@ begin
is_intermission => is_intermission, -- OUT
is_suspend => is_suspend, -- OUT
is_error => is_error, -- OUT
is_overload => is_overload, -- OUT
is_overload => is_overload_i, -- OUT
-- TXT Buffers interface
tran_word => tran_word, -- IN
......@@ -815,7 +818,7 @@ begin
-- 2. Looped back dominant Bit for Bus monitoring Mode.
-- 3. Regular RX Data
---------------------------------------------------------------------------
bds_data_in <= bst_data_out when (sp_control = SECONDARY_SAMPLE) else
bds_data_in <= bst_data_out when (sp_control_i = SECONDARY_SAMPLE) else
lpb_dominant when (drv_bus_mon_ena = '1') else
rx_data_wbs;
......@@ -894,7 +897,7 @@ begin
is_error;
stat_bus(STAT_PC_IS_OVERLOAD_INDEX) <=
is_overload;
is_overload_i;
stat_bus(STAT_ARB_LOST_INDEX) <=
arbitration_lost_i;
......@@ -1070,7 +1073,7 @@ begin
error_warning_limit_i;
stat_bus(STAT_ERROR_VALID_INDEX) <=
err_detected;
err_detected_i;
stat_bus(STAT_ACK_RECIEVED_OUT_INDEX) <=
ack_received_i;
......@@ -1112,5 +1115,6 @@ begin
trv_delay_calib <= trv_delay_calib_i;
is_bus_off <= is_bus_off_i;
sof_pulse <= sof_pulse_i;
is_overload <= is_overload_i;
end architecture;
\ No newline at end of file
......@@ -417,6 +417,9 @@ architecture rtl of can_top_level is
-- Bit Rate Was Shifted
signal br_shifted : std_logic;
-- Overload frame is being transmitted
signal is_overload : std_logic;
------------------------------------------------------------------------
-- CAN Core <-> Prescaler Interface
------------------------------------------------------------------------
......@@ -735,6 +738,7 @@ begin
rx_full => rx_full, -- IN
rx_empty => rx_empty, -- IN
txtb_hw_cmd_int => txtb_hw_cmd_int, -- IN
is_overload => is_overload, -- IN
-- Memory registers Interface
drv_bus => drv_bus, -- IN
......@@ -801,6 +805,7 @@ begin
err_detected => err_detected, -- OUT
error_passive_changed => error_passive_changed, -- OUT
error_warning_limit => error_warning_limit, -- OUT
is_overload => is_overload, -- OUT
-- Prescaler interface
rx_triggers => rx_triggers, -- IN
......
This diff is collapsed.
......@@ -145,6 +145,9 @@ entity int_manager is
-- HW command on TXT Buffers interrupt
txtb_hw_cmd_int :in std_logic_vector(G_TXT_BUFFER_COUNT - 1 downto 0);
-- Overload frame is being transmitted
is_overload :in std_logic;
------------------------------------------------------------------------
-- Memory registers Interface
......@@ -255,8 +258,8 @@ begin
int_input_active(RBNEI_IND) <= not rx_empty;
int_input_active(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int);
-- Logger finished interrupt removed after logger was thrown out!
int_input_active(7) <= '0';
-- Overload frame interrupt
int_input_active(OFI_IND) <= is_overload;
---------------------------------------------------------------------------
-- Interrupt module instances
......@@ -370,4 +373,11 @@ begin
-- psl txbhci_enable_cov : cover
-- (int_vect_i(TXBHCI_IND) = '1' and int_ena(TXBHCI_IND) = '1');
-- psl ofi_int_set_cov : cover
-- {int_vect_i(OFI_IND) = '0';int_vect_i(OFI_IND) = '1'};
-- psl ofi_enable_cov : cover
-- (int_vect_i(OFI_IND) = '1' and int_ena(OFI_IND) = '1');
end architecture;
\ No newline at end of file
......@@ -1442,6 +1442,7 @@ package can_components is
-- Overload frame is being transmitted
is_overload :out std_logic;
-----------------------------------------------------------------------
-- Data-path interface
-----------------------------------------------------------------------
......@@ -2524,6 +2525,9 @@ package can_components is
-- Error warning limit reached
error_warning_limit :out std_logic;
-- Overload frame is being transmitted
is_overload :out std_logic;
------------------------------------------------------------------------
-- Prescaler interface
......@@ -2761,6 +2765,9 @@ package can_components is
-- HW command on TXT Buffers interrupt
txtb_hw_cmd_int :in std_logic_vector(G_TXT_BUFFER_COUNT - 1 downto 0);
-- Overload frame is being transmitted
is_overload :in std_logic;
------------------------------------------------------------------------
-- Memory registers Interface
......
......@@ -624,6 +624,7 @@ package can_fd_register_map is
constant EPI_IND : natural := 4;
constant ALI_IND : natural := 5;
constant BEI_IND : natural := 6;
constant OFI_IND : natural := 7;
constant RXFI_IND : natural := 8;
constant BSI_IND : natural := 9;
constant RBNEI_IND : natural := 10;
......@@ -640,6 +641,7 @@ package can_fd_register_map is
constant RXFI_RSTVAL : std_logic := '0';
constant BSI_RSTVAL : std_logic := '0';
constant RBNEI_RSTVAL : std_logic := '0';
constant OFI_RSTVAL : std_logic := '0';
constant TXBHCI_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
......
......@@ -182,10 +182,10 @@ begin
int_stat_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111101111111" ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111101111111"
auto_clear => "0000111111111111"
)
port map(
clk_sys => clk_sys ,-- in
......
......@@ -311,6 +311,9 @@ architecture rtl of resynchronisation is
-- SJW more than 0
signal sjw_mt_zero : std_logic;
-- Choose basic segment length
signal use_basic_segm_length : std_logic;
begin
......@@ -329,6 +332,7 @@ begin
resize(unsigned(tseg_2), C_BS_WIDTH);
segm_extension <=
to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1') else
resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else
resize(unsigned(bt_counter), C_EXT_WIDTH);
......@@ -338,19 +342,37 @@ begin
segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) -
resize(segm_extension, C_EXP_WIDTH);
sync_segm_length <= segm_ext_sub when (is_tseg2 = '1') else
sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1')
else
segm_ext_add;
---------------------------------------------------------------------------
-- Use basic segment length:
-- 1. Circuit start
-- 2. Segment end, but not due to hard-sync. When segment end due to hard
-- sync occurs, we must take TSEG1 - 1 which is calculated in synced
-- segment length!
---------------------------------------------------------------------------
use_basic_segm_length <= '1' when (start_edge = '1')
else
'1' when (segm_end = '1' and
h_sync_valid = '0')
else
'0';
---------------------------------------------------------------------------
-- Expected length of segment register. Load:
-- 1. Nominal length of next segment
-- 2. Value post-resynchronisation.
-- 2. Value post-synchronisation.
---------------------------------------------------------------------------
exp_seg_length_d <=
resize(basic_segm_length, C_EXP_WIDTH) when (segm_end = '1' or start_edge = '1') else
resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')
else
resize(sync_segm_length, C_EXP_WIDTH);
exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or
exp_seg_length_ce <= '1' when (segm_end = '1' or
resync_edge_valid = '1' or
h_sync_valid = '1' or
start_edge = '1')
else
'0';
......
......@@ -3,27 +3,12 @@ proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "logger_size" -parent ${Page_0}
ipgui::add_param $IPINST -name "rx_buffer_size" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_be" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_filtA" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_filtB" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_filtC" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_range" -parent ${Page_0}
ipgui::add_param $IPINST -name "tx_time_sup" -parent ${Page_0}
ipgui::add_param $IPINST -name "use_logger" -parent ${Page_0}
ipgui::add_param $IPINST -name "use_sync" -parent ${Page_0}
}
proc update_PARAM_VALUE.logger_size { PARAM_VALUE.logger_size } {
# Procedure called to update logger_size when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.logger_size { PARAM_VALUE.logger_size } {
# Procedure called to validate logger_size
return true
}
proc update_PARAM_VALUE.rx_buffer_size { PARAM_VALUE.rx_buffer_size } {
......@@ -35,15 +20,6 @@ proc validate_PARAM_VALUE.rx_buffer_size { PARAM_VALUE.rx_buffer_size } {
return true
}
proc update_PARAM_VALUE.sup_be { PARAM_VALUE.sup_be } {
# Procedure called to update sup_be when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.sup_be { PARAM_VALUE.sup_be } {
# Procedure called to validate sup_be
return true
}
proc update_PARAM_VALUE.sup_filtA { PARAM_VALUE.sup_filtA } {
# Procedure called to update sup_filtA when any of the dependent parameters in the arguments change
}
......@@ -80,49 +56,11 @@ proc validate_PARAM_VALUE.sup_range { PARAM_VALUE.sup_range } {
return true
}
proc update_PARAM_VALUE.tx_time_sup { PARAM_VALUE.tx_time_sup } {
# Procedure called to update tx_time_sup when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.tx_time_sup { PARAM_VALUE.tx_time_sup } {
# Procedure called to validate tx_time_sup
return true
}
proc update_PARAM_VALUE.use_logger { PARAM_VALUE.use_logger } {
# Procedure called to update use_logger when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.use_logger { PARAM_VALUE.use_logger } {
# Procedure called to validate use_logger
return true
}
proc update_PARAM_VALUE.use_sync { PARAM_VALUE.use_sync } {
# Procedure called to update use_sync when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.use_sync { PARAM_VALUE.use_sync } {
# Procedure called to validate use_sync
return true
}
proc update_MODELPARAM_VALUE.use_logger { MODELPARAM_VALUE.use_logger PARAM_VALUE.use_logger } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.use_logger}] ${MODELPARAM_VALUE.use_logger}
}
proc update_MODELPARAM_VALUE.rx_buffer_size { MODELPARAM_VALUE.rx_buffer_size PARAM_VALUE.rx_buffer_size } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.rx_buffer_size}] ${MODELPARAM_VALUE.rx_buffer_size}
}
proc update_MODELPARAM_VALUE.use_sync { MODELPARAM_VALUE.use_sync PARAM_VALUE.use_sync } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.use_sync}] ${MODELPARAM_VALUE.use_sync}
}
proc update_MODELPARAM_VALUE.sup_filtA { MODELPARAM_VALUE.sup_filtA PARAM_VALUE.sup_filtA } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.sup_filtA}] ${MODELPARAM_VALUE.sup_filtA}
......@@ -142,19 +80,3 @@ proc update_MODELPARAM_VALUE.sup_range { MODELPARAM_VALUE.sup_range PARAM_VALUE.
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.sup_range}] ${MODELPARAM_VALUE.sup_range}
}
proc update_MODELPARAM_VALUE.tx_time_sup { MODELPARAM_VALUE.tx_time_sup PARAM_VALUE.tx_time_sup } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.tx_time_sup}] ${MODELPARAM_VALUE.tx_time_sup}
}
proc update_MODELPARAM_VALUE.sup_be { MODELPARAM_VALUE.sup_be PARAM_VALUE.sup_be } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.sup_be}] ${MODELPARAM_VALUE.sup_be}
}
proc update_MODELPARAM_VALUE.logger_size { MODELPARAM_VALUE.logger_size PARAM_VALUE.logger_size } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.logger_size}] ${MODELPARAM_VALUE.logger_size}
}
......@@ -249,7 +249,6 @@ architecture func of prescaler_model is
begin
exp_duration <= nom_dur;
i <= 0;
wait for 0 ns;
while (i < exp_duration) loop
......@@ -493,6 +492,17 @@ begin
bt_fsm_i <= s_bt_tseg1;
-------------------------------------------------------------------
-- If Hard synchronisation occured and we are here, TSEG1 must
-- start from 1, not zero, since we skip SYNC segment!
-------------------------------------------------------------------
if (h_sync_occured_tseg1.get) then
tseg1_i <= 1;
else
tseg1_i <= 0;
end if;
wait for 0 ns;
-- Execute segment 1
count_segment (
clk_sys => clk_sys,
......@@ -568,6 +578,8 @@ begin
if (drv_ena = '1') then
wait until tseg2_nbt_req = true;
tseg2_nbt_ack <= false;
tseg2_nbt_i <= 0;
wait for 0 ns;
count_segment (
clk_sys => clk_sys,
......@@ -584,7 +596,7 @@ begin
h_sync_occured => h_sync_occured_tseg2_nbt,
edge_occured => edge_occured_tseg2_nbt
);
if (drv_ena = '1' and sp_control = NOMINAL_SAMPLE) then
tseg2_nbt_ack <= true;
end if;
......@@ -610,6 +622,8 @@ begin
if (drv_ena = '1') then
wait until tseg2_dbt_req = true;
tseg2_dbt_ack <= false;
tseg2_dbt_i <= 0;
wait for 0 ns;
count_segment (
clk_sys => clk_sys,
......
......@@ -254,6 +254,11 @@ architecture bit_stuffing_unit_test of CAN_test is
-- LCOV_EXCL_STOP
end if;
-- Set previous bit to actual input of Bit stuffing. This corresponds
-- to previously propagated bit value when bit stuffing was not yet
-- enabled!
prev_bit := tx_data;
--------------------------------------
-- Calculate non-fixed stuffing
--------------------------------------
......
......@@ -100,6 +100,9 @@ architecture int_man_unit_test of CAN_test is
-- HW command on TX Buffer
signal txtb_hw_cmd_int : std_logic_vector(C_TXT_BUFFER_COUNT - 1 downto 0);
-- Overload frame is being transmitted
signal is_overload : std_logic;
----------------------------------------------
-- Status signals
----------------------------------------------
......@@ -181,8 +184,10 @@ architecture int_man_unit_test of CAN_test is
signal rx_empty :inout std_logic;
-- TXT HW Command
signal txtb_hw_cmd_int :inout std_logic_vector(C_TXT_BUFFER_COUNT - 1
downto 0)
signal txtb_hw_cmd_int :inout std_logic_vector(C_TXT_BUFFER_COUNT - 1
downto 0);
signal is_overload :inout std_logic
)is
variable tmp : std_logic;
begin
......@@ -245,6 +250,12 @@ architecture int_man_unit_test of CAN_test is
else
rand_logic_s(rand_ctr, rx_empty, 0.05);
end if;
if (is_overload = '1') then
rand_logic_s(rand_ctr, is_overload, 0.95);
else
rand_logic_s(rand_ctr, is_overload, 0.05);
end if;
for i in 0 to C_TXT_BUFFER_COUNT - 1 loop
if (txtb_hw_cmd_int(i) = '1') then
......@@ -326,6 +337,7 @@ begin
rx_data_overrun => rx_data_overrun ,
rec_valid => rec_valid ,
rx_full => rx_full,
is_overload => is_overload,
drv_bus => drv_bus ,
int => int,
int_vector => int_vector,
......@@ -344,6 +356,7 @@ begin
int_input(RXFI_IND) <= rx_full;
int_input(BSI_IND) <= br_shifted;
int_input(RBNEI_IND) <= not rx_empty;
int_input(OFI_IND) <= is_overload;
int_input(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int);
......@@ -369,7 +382,7 @@ begin
generate_sources(rand_ctr_1, err_detected, error_passive_changed ,
error_warning_limit , arbitration_lost, tran_valid,
br_shifted, rx_data_overrun , rec_valid ,
rx_full , rx_empty, txtb_hw_cmd_int);
rx_full , rx_empty, txtb_hw_cmd_int, is_overload);
end loop;
end process;
......