...
 
Commits (16)
image: mjerabek/ghdl:upstream-gcc
image: registry.gitlab.com/canfd/server-tools/ghdl
before_script:
- "export PATH=/opt/ghdl/bin:$PATH"
- export LC_ALL=C.UTF-8
......@@ -48,16 +48,11 @@ build_driver:
build_doc:
stage: build
tags: [virt] # runner in virtual, without docker, with new lyx
only:
- master
- tags
- web # debug only!
#image: hathi.duckdns.org/user/lyx:buster
only: *only
image: registry.gitlab.com/canfd/server-tools/lyx
script:
- export LC_ALL=en_US.UTF-8
- export LANG=en_US.UTF-8
- export TMPDIR=/var/tmp # not enouhg room in tmpfs
- make -C doc/core
artifacts:
paths:
......@@ -66,7 +61,7 @@ build_doc:
build_linux_driver:
stage: build
only: *only
image: hathi.duckdns.org/user/ctucanfd_drvtest
image: registry.gitlab.com/canfd/server-tools/ctucanfd_drvtest
script:
- cd driver/linux
- "make -j`nproc` KDIR=/linux/build"
......
all: Progdokum.pdf
Progdokum.pdf: version.tex
lyx --export-to pdf Progdokum.pdf Progdokum.lyx
#lyx --export-to pdf Progdokum.pdf Progdokum.lyx
lyx --export-to latex Progdokum.tex Progdokum.lyx
sed -rie '/\{inputenc\}/d' Progdokum.tex
iconv -f latin2 -t utf8 <Progdokum.tex >Progdokum.tex-1 && mv Progdokum.tex-1 Progdokum.tex
xelatex Progdokum
# run again to generate PDF outline and references
xelatex Progdokum
xelatex Progdokum
version.tex: FORCE
desc=$$(git describe --always); \
......
#!/bin/bash
#IMG=mjerabek/lyx:buster
IMG=hathi.duckdns.org/user/lyx:buster
IMG=registry.gitlab.com/canfd/server-tools/lyx
d=$(realpath $(dirname "$0")/../..)
docker run --rm -v $d:/build -w /build/modules/CTU_CAN_FD/doc/core $IMG make
#docker run -ti --rm -v $d:/build -w /build/modules/CTU_CAN_FD/doc/core $IMG
docker run --rm -v $d:/build -w /build/modules/CTU_CAN_FD/doc/core -e HOME=/tmp -u $UID:$UID $IMG make clean all
......@@ -13,6 +13,8 @@ if [ -d /build ]; then
export LC_ALL=C.UTF-8
export LANG=C.UTF-8
export PYTHONUNBUFFERED=1
export HOME=$(mktemp -d /tmp/home.XXXXX)
cd /build/test
if [ $# -gt 0 ]; then
exec "$@"
......@@ -20,6 +22,8 @@ if [ -d /build ]; then
exec bash
fi
else
docker run --rm -ti -v $PWD:/build mjerabek/ghdl:upstream-gcc /build/run-docker-test "$@"
d="$(realpath "$(dirname "$0")")"
#"
docker run --rm -ti -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v "$d:/build" --user $(id -u):$(id -g) registry.gitlab.com/canfd/server-tools/ghdl:gtkwave /build/run-docker-test "$@"
fi
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Detects bit error.
--------------------------------------------------------------------------------
-- 28.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity bit_errror_detector is
generic(
-- Reset polarity
constant reset_polarity : std_logic
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Bit error detection enabled
signal bit_err_enable :in std_logic;
-- Core is enabled
signal drv_ena :in std_logic;
-- Sample control (nominal, data, secondary)
signal sp_control :in std_logic_vector(1 downto 0);
-- Input sample signals
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
-----------------------------------------------------------------------
-- TX Data inputs
-----------------------------------------------------------------------
-- Regulary transmitted data
signal data_tx :in std_logic;
-- Delayed transmitted data (for detection in secondary sampling point)
signal data_tx_delayed :in std_logic;
-----------------------------------------------------------------------
-- RX Data inputs
-----------------------------------------------------------------------
-- Receieved data in Nominal Bit time (either directly sampled data,
-- or tripple sampling output)
signal data_rx_nbt :in std_logic;
-- Received data (Nominal and Data)
signal can_rx_i :in std_logic;
------------------------------------------------------------------------
-- Bit error output
------------------------------------------------------------------------
signal bit_error : out std_logic
);
end entity;
architecture rtl of bit_errror_detector is
-- Internal sample signal (muxed for NBT, DBT and SAMPLE)
signal sample : std_logic;
-- Expected bit value (TX, from SYNC)
signal exp_data : std_logic;
-- Actual data value (RX, from Sample point)
signal act_data : std_logic;
-- Bit error detected value
signal bit_error_d : std_logic;
signal bit_error_q : std_logic;
begin
----------------------------------------------------------------------------
-- Sample point multiplexor
----------------------------------------------------------------------------
sample <= sample_nbt when (sp_control = NOMINAL_SAMPLE) else
sample_dbt when (sp_control = DATA_SAMPLE) else
sample_sec when (sp_control = SECONDARY_SAMPLE) else
'0';
----------------------------------------------------------------------------
-- Expected data mux. Choose between TX data and delayed TX Data
----------------------------------------------------------------------------
exp_data <= data_tx_delayed when (sp_control = SECONDARY_SAMPLE) else
data_tx;
----------------------------------------------------------------------------
-- Actual data. Consider tripple sampling for Nominal Bit-rate
----------------------------------------------------------------------------
act_data <= data_rx_nbt when (sp_control = NOMINAL_SAMPLE) else
can_rx_i;
----------------------------------------------------------------------------
-- Bit Error detection. If expected data is not equal to actual data in
-- sample point -> Bit Error!
----------------------------------------------------------------------------
bit_error_d <= '0' when (drv_ena = CTU_CAN_DISABLED or bit_err_enable = '0') else
'1' when (exp_data /= act_data and sample = '1') else
'0' when (exp_data = act_data and sample = '1') else
bit_error_q;
----------------------------------------------------------------------------
-- Bit error register
----------------------------------------------------------------------------
bit_error_reg_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
bit_error_q <= '0';
elsif (rising_edge(clk_sys)) then
bit_error_q <= bit_error_d;
end if;
end process;
-- Propagation to output
bit_error <= bit_error_q;
end architecture;
\ No newline at end of file
......@@ -117,7 +117,10 @@ entity bus_sampling is
-- Turn off only when Synthetizer puts synchronisation chain automati-
-- cally on the output pins! Otherwise metastability issues will occur!
------------------------------------------------------------------------
constant use_Sync : boolean := false
constant use_Sync : boolean := false;
-- Reset polarity
constant reset_polarity : std_logic := '0'
);
PORT(
------------------------------------------------------------------------
......@@ -266,7 +269,7 @@ architecture rtl of bus_sampling is
-- Delayed TX Data from TX Data shift register at position of secondary
-- sampling point.
signal tx_data_delayed : std_logic;
signal data_tx_delayed : std_logic;
-- Shift Register for generating secondary sampling signal
signal sample_sec_shift : std_logic_vector
......@@ -466,7 +469,7 @@ begin
write => sample_dbt,
read => sample_sec,
data_in => data_tx,
data_out => tx_data_delayed
data_out => data_tx_delayed
);
......@@ -537,134 +540,50 @@ begin
data_rx_nbt <= CAN_rx_trs_majority when (drv_sam = TSM_ENABLE) else
CAN_rx_i;
---------------------------------------------------------------------------
-- Bit error detector
---------------------------------------------------------------------------
bit_errror_detector_comp : bit_errror_detector
generic map(
reset_polarity => reset_polarity
)
port map(
clk_sys => clk_sys,
res_n => res_n,
bit_err_enable => bit_err_enable,
drv_ena => drv_ena,
sp_control => sp_control,
sample_nbt => sample_nbt,
sample_dbt => sample_dbt,
sample_sec => sample_sec,
data_tx => data_tx,
data_tx_delayed => data_tx_delayed,
data_rx_nbt => data_rx_nbt,
can_rx_i => can_rx_i,
bit_error => bit_Error_reg
);
----------------------------------------------------------------------------
-- Sampling of bus value
----------------------------------------------------------------------------
sample_proc : process(res_n, clk_sys)
begin
if (res_n = ACT_RESET) then
prev_Sample <= RECESSIVE;
elsif rising_edge(clk_sys) then
if (drv_ena = CTU_CAN_ENABLED) then
case sp_control is
----------------------------------------------------------------
-- Sampling with Nominal Bit Time
-- (normal CAN, transceiver, receiver)
--
-- Tripple sampling option selects the majority from last
-- three sampled values
----------------------------------------------------------------
when NOMINAL_SAMPLE =>
if (sample_nbt = '1') then
prev_Sample <= data_rx_nbt;
end if;
----------------------------------------------------------------
-- Sampling with Data Bit Time (CAN FD, reciever).
----------------------------------------------------------------
when DATA_SAMPLE =>
if (sample_dbt = '1') then
prev_Sample <= CAN_rx_i;
end if;
----------------------------------------------------------------
-- Sampling with Secondary sampling point.
-- (CAN FD, transciever)
----------------------------------------------------------------
when SECONDARY_SAMPLE =>
if (sample_sec = '1') then
prev_Sample <= CAN_rx_i;
end if;
when others =>
prev_Sample <= prev_Sample;
end case;
end if;
end if;
end process sample_proc;
----------------------------------------------------------------------------
-- Bit Error detection process
----------------------------------------------------------------------------
bit_err_detect_proc : process(res_n, clk_sys)
begin
if (res_n = ACT_RESET) then
bit_Error_reg <= '0';
elsif rising_edge(clk_sys) then
if (drv_ena = CTU_CAN_ENABLED and bit_err_enable = '1') then
case sp_control is
----------------------------------------------------------------
-- Sampling with nominal bit time
-- (normal CAN, transciever, reciever)
----------------------------------------------------------------
when NOMINAL_SAMPLE =>
if (sample_nbt = '1') then
-- If TX data are equal to RX Data -> No problem.
if (data_rx_nbt = data_tx) then
bit_Error_reg <= '0';
else
bit_Error_reg <= '1';
end if;
end if;
----------------------------------------------------------------
-- Sampling with data bit time (CAN FD, reciever)
----------------------------------------------------------------
when DATA_SAMPLE =>
if (sample_dbt = '1') then
--Bit Error detection when sampling
if (CAN_rx_i = data_tx) then
bit_Error_reg <= '0';
else
bit_Error_reg <= '1';
end if;
end if;
----------------------------------------------------------------
-- Sampling with transciever delay compensation
-- (CAN FD, transciever)
----------------------------------------------------------------
when SECONDARY_SAMPLE =>
if (sample_sec = '1') then
-- Bit Error comparison differs in this case, not actual
-- transmitted bit is compared, but delayed bit is
-- compared (in ssp_shift register)
if (CAN_rx_i = tx_data_delayed) then
bit_Error_reg <= '0';
else
bit_Error_reg <= '1';
end if;
end if;
when others =>
end case;
-- If whole Core is disabled, or Bit Error detection is disabled,
-- hold permanently in zero!
else
bit_Error_reg <= '0';
end if;
end if;
end process bit_err_detect_proc;
-- Propagating sampled data to CAN Core
data_rx <= prev_Sample;
sample_mux_comp : sample_mux
generic map(
reset_polarity => reset_polarity,
pipeline_sampled_data => true
)
port map(
clk_sys => clk_sys,
res_n => res_n,
drv_ena => drv_ena,
sp_control => sp_control,
sample_nbt => sample_nbt,
sample_dbt => sample_dbt,
sample_sec => sample_sec,
data_rx_nbt => data_rx_nbt,
can_rx_i => can_rx_i,
prev_sample => prev_sample,
data_rx => data_rx
);
--Output data propagation
CAN_tx <= data_tx;
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Detects bit error.
--------------------------------------------------------------------------------
-- 28.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity sample_mux is
generic(
-- Reset polarity
constant reset_polarity : std_logic;
-- Pipeline data output
constant pipeline_sampled_data : boolean := true
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- CTU CAN FD enabled
signal drv_ena :in std_logic;
-- Sample control (nominal, data, secondary)
signal sp_control :in std_logic_vector(1 downto 0);
-- Input sample signals
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
-----------------------------------------------------------------------
-- RX Data inputs
-----------------------------------------------------------------------
-- Receieved data in Nominal Bit time (either directly sampled data,
-- or tripple sampling output)
signal data_rx_nbt :in std_logic;
-- Received data (Nominal and Data)
signal can_rx_i :in std_logic;
------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------
-- Sampled value of RX in Sample point (DFF output)
signal prev_sample : out std_logic;
-- Sampled value of RX in Sample point (either DFF or direct output)
signal data_rx : out std_logic
);
end entity;
architecture rtl of sample_mux is
-- Internal sample signal (muxed for NBT, DBT and SAMPLE)
signal sample : std_logic;
-- RX Data
signal rx_data_i : std_logic;
-- Bit error detected value
signal sample_prev_d : std_logic;
signal sample_prev_q : std_logic;
begin
----------------------------------------------------------------------------
-- Sample point multiplexor
----------------------------------------------------------------------------
sample <= sample_nbt when (sp_control = NOMINAL_SAMPLE) else
sample_dbt when (sp_control = DATA_SAMPLE) else
sample_sec when (sp_control = SECONDARY_SAMPLE) else
'0';
----------------------------------------------------------------------------
-- RX data mux.
----------------------------------------------------------------------------
rx_data_i <= data_rx_nbt when (sp_control = NOMINAL_SAMPLE) else
can_rx_i;
----------------------------------------------------------------------------
-- Previous sample register
----------------------------------------------------------------------------
sample_prev_d <= rx_data_i when (sample = '1') else
sample_prev_q;
sample_prev_req_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
sample_prev_q <= RECESSIVE;
elsif (rising_edge(clk_sys)) then
if (drv_ena = '1') then
sample_prev_q <= sample_prev_d;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Receive data. If pipeline is inserted, then use directly sample_prev,
-- if not, then pipe the input to output directly!
----------------------------------------------------------------------------
insert_pipeline_true_gen : if (pipeline_sampled_data = true) generate
data_rx <= sample_prev_q;
end generate insert_pipeline_true_gen;
insert_pipeline_false_gen : if (pipeline_sampled_data = false) generate
data_rx <= rx_data_i;
end generate insert_pipeline_false_gen;
end architecture;
\ No newline at end of file
......@@ -804,7 +804,8 @@ begin
bus_sampling_comp : bus_sampling
generic map (
use_Sync => use_sync
use_Sync => use_sync,
reset_polarity => ACT_RESET
)
port map(
clk_sys => clk_sys,
......
......@@ -542,6 +542,12 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bit_error_detector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bus_sampling.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -554,6 +560,12 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/sample_mux.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/trv_delay_meas.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -913,6 +925,13 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bit_error_detector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bus_sampling.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -927,6 +946,13 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/sample_mux.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/trv_delay_meas.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......
......@@ -729,7 +729,8 @@ package can_components is
----------------------------------------------------------------------------
component bus_sampling is
generic (
use_Sync : boolean
use_Sync : boolean;
reset_polarity : std_logic
);
port(
signal clk_sys : in std_logic;
......@@ -819,6 +820,26 @@ package can_components is
);
end component;
component sample_mux is
generic(
constant reset_polarity : std_logic;
constant pipeline_sampled_data : boolean := true
);
port(
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal drv_ena :in std_logic;
signal sp_control :in std_logic_vector(1 downto 0);
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
signal data_rx_nbt :in std_logic;
signal can_rx_i :in std_logic;
signal prev_sample :out std_logic;
signal data_rx :out std_logic
);
end component sample_mux;
----------------------------------------------------------------------------
-- Event Logger module
----------------------------------------------------------------------------
......@@ -843,6 +864,27 @@ package can_components is
signal log_state_out : out logger_state_type
);
end component;
component bit_errror_detector is
generic(
constant reset_polarity : std_logic
);
port(
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal bit_err_enable :in std_logic;
signal drv_ena :in std_logic;
signal sp_control :in std_logic_vector(1 downto 0);
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
signal data_tx :in std_logic;
signal data_tx_delayed :in std_logic;
signal data_rx_nbt :in std_logic;
signal can_rx_i :in std_logic;
signal bit_error :out std_logic
);
end component;
----------------------------------------------------------------------------
......
......@@ -586,5 +586,73 @@ begin
end if;
end process;
------------------------------------------------------------------------------
-- Functional coverage
------------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
-- psl txt_lock_cov : cover
-- (txt_hw_cmd.lock = '1');
--
-- psl txt_unlock_cov : cover
-- (txt_hw_cmd.unlock = '1');
--
-- psl txt_lock_buf_1_cov : cover
-- (txt_hw_cmd_buf_index = 0 and txt_hw_cmd.lock = '1');
--
-- psl txt_lock_buf_2_cov : cover
-- (txt_hw_cmd_buf_index = 1 and txt_hw_cmd.lock = '1');
--
-- psl txt_lock_buf_3_cov : cover
-- (txt_hw_cmd_buf_index = 2 and txt_hw_cmd.lock = '1');
--
-- psl txt_lock_buf_4_cov : cover
-- (txt_hw_cmd_buf_index = 3 and txt_hw_cmd.lock = '1');
--
-- psl txt_prio_change_cov : cover
-- {select_buf_avail = '1';
-- select_buf_avail = '1' and select_buf_index'active;
-- select_buf_avail = '1'};
--
-- Here it is enough to make sure that two concrete buffers with the
-- same priority are ready! Here we only test the proper index selection
-- in case of equal priorities!
-- psl txt_buf_eq_priority_cov : cover
-- (txt_buf_ready(0) = '1' and txt_buf_ready(1) = '1' and
-- txt_buf_prio(0) = txt_buf_prio(1))
-- report "Selected Buffer index changed while buffer selected";
--
-- Change of buffer from Ready to not Ready but not due to lock (e.g.
-- set abort). Again one buffer is enough!
-- psl buf_ready_to_not_ready_cov : cover
-- {txt_buf_ready(0) = '1' and select_buf_index = 0 and
-- txt_hw_cmd.lock = '0'; txt_buf_ready(0) = '0'}
-- report "Buffer became non-ready but not due to lock command";
--
-- psl txt_buf_all_ready_cov : cover
-- (txt_buf_ready(0) = '1' and txt_buf_ready(1) = '1' and
-- txt_buf_ready(2) = '1' and txt_buf_ready(3) = '1')
-- report "All TXT Buffers ready";
--
-- psl txt_buf_change_cov : cover
-- (txtb_changed = '1' and txt_hw_cmd.lock = '1')
-- report "TX Buffer changed between two frames";
--
-- psl txt_buf_sim_chng_and_lock_cov : cover
-- (select_index_changed = '1' and txt_hw_cmd.lock = '1');
-----------------------------------------------------------------------------
-- Assertions
-----------------------------------------------------------------------------
-- When TXT Buffer is not ready for more than one cycle, LOCK command might
-- not occur. If it is not ready for one clock cycle, it might still be
-- due to set abort and LOCK command applied simultaneously. This is OK.
-- But as soon as buffer is not ready for second cycle, LOCK command can't
-- be active!
--
-- psl txtb_no_lock_when_not_ready_asrt : assert never
-- {tran_frame_valid_out = '0';
-- tran_frame_valid_out = '0' and txt_hw_cmd.lock = '1'}
-- report "NO TXT Buffer ready and lock occurs!" severity error;
-----------------------------------------------------------------------------
end architecture;
......@@ -291,21 +291,14 @@ begin
store_last_txtb_index <= '1';
------------------------------------------------------------------------
-- Keep the arbitrator in selection of the lowest word as
-- long as there is no buffer with valid frame.
-- If Selected buffer changes, restart the selection.
-- Restart the selection if one of following occurs:
-- 1. Selected Buffer changed.
-- 2. There is not buffer marked as ready -> Hold in not selected!
------------------------------------------------------------------------
elsif ((select_buf_avail = '0')) then
elsif (select_buf_avail = '0' or select_index_changed = '1') then
load_ts_lw_addr <= '1';
frame_valid_com_clear <= '1';
------------------------------------------------------------------------
-- Selected buffer index on the output of priority decoder has changed
-- during selection. Restart the selection!
------------------------------------------------------------------------
elsif (select_index_changed = '1') then
load_ts_lw_addr <= '1';
else
case tx_arb_fsm is
......@@ -353,7 +346,16 @@ begin
end case;
end if;
end process;
------------------------------------------------------------------------------
-- Functional coverage
------------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
--
-- psl txt_buf_wait_till_timestamp_cov : cover
-- (tx_arb_fsm = arb_sel_upp_ts and fsm_wait_state = false and
-- timestamp_valid = '0')
-- report "TXT Buffer waiting for Timestamp to reach TX Time";
end architecture;
......@@ -41,11 +41,12 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Transmitt Message Buffer FSM.
-- Transmitt Frame Buffer FSM.
--------------------------------------------------------------------------------
-- Revision History:
--
-- 07.11.2018 Created file
-- 27.02.2019 Added PSL assertions.
--------------------------------------------------------------------------------
Library ieee;
......@@ -119,8 +120,14 @@ architecture rtl of txt_buffer_fsm is
-- FSM state of the buffer
signal buf_fsm : txt_fsm_type;
-- Abort command applied
signal abort_applied : std_logic;
begin
abort_applied <= '1' when (txt_sw_cmd.set_abt = '1' and sw_cbs = '1') else
'0';
----------------------------------------------------------------------------
-- Buffer FSM process
----------------------------------------------------------------------------
......@@ -163,7 +170,7 @@ begin
end if;
-- Abort the ready buffer
elsif (txt_sw_cmd.set_abt = '1' and sw_cbs = '1') then
elsif (abort_applied = '1') then
buf_fsm <= txt_aborted;
else
buf_fsm <= buf_fsm;
......@@ -191,7 +198,7 @@ begin
end if;
-- Request abort during transmission
elsif (txt_sw_cmd.set_abt = '1' and sw_cbs = '1') then
elsif (abort_applied = '1') then
buf_fsm <= txt_ab_prog;
else
buf_fsm <= buf_fsm;
......@@ -307,10 +314,10 @@ begin
'0';
-- Buffer is ready for selection by TX Arbitrator only in state "Ready"
-- Abort signal must not be active. If not considered,
-- race conditions between HW and SW commands could occur.
-- Abort signal must not be active. If not considered, race condition
-- between HW and SW commands could occur!
txt_buf_ready <= '1' when ((buf_fsm = txt_ready) and
(txt_sw_cmd.set_abt = '0'))
(abort_applied = '0'))
else
'0';
......@@ -323,65 +330,55 @@ begin
TXT_ERR when txt_error,
TXT_ABT when txt_aborted,
TXT_ETY when txt_empty;
----------------------------------------------------------------------------
-- Monitoring invalid command combinations!
----------------------------------------------------------------------------
lock_check_proc : process(clk_sys)
begin
if (rising_edge(clk_sys)) then
if (txt_hw_cmd.lock = '1' and
buf_fsm /= txt_ready and
hw_cbs = '1')
then
report "Buffer not READY and LOCK occurred on TXT Buffer: " &
integer'image(ID) & " Buffer state: " &
txt_fsm_type'image(buf_fsm) severity error;
end if;
end if;
end process;
unlock_check_proc : process(clk_sys)
begin
if (rising_edge(clk_sys)) then
if (txt_hw_cmd.unlock = '1' and
buf_fsm /= txt_tx_prog and
buf_fsm /= txt_ab_prog and
hw_cbs = '1')
then
report "Buffer not 'TX_prog' or 'AB_prog' and UNLOCK" &
" occurred on Buffer: " & integer'image(ID) severity error;
end if;
end if;
end process;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Functional coverage
----------------------------------------------------------------------------
----------------------------------------------------------------------------
func_cov_block : block
begin
-- psl default clock is rising_edge(clk_sys);
-- Each FSM state
-- psl txtb_fsm_empty : cover (buf_fsm = txt_empty);
-- psl txtb_fsm_ready : cover (buf_fsm = txt_ready);
-- psl txtb_fsm_tx_prog : cover (buf_fsm = txt_tx_prog);
-- psl txtb_fsm_ab_prog : cover (buf_fsm = txt_ab_prog);
-- psl txtb_fsm_error : cover (buf_fsm = txt_error);
-- psl txtb_fsm_aborted : cover (buf_fsm = txt_aborted);
-- psl txtb_fsm_tx_ok : cover (buf_fsm = txt_ok);
-- psl txtb_fsm_empty_cov : cover (buf_fsm = txt_empty);
-- psl txtb_fsm_ready_cov : cover (buf_fsm = txt_ready);
-- psl txtb_fsm_tx_prog_cov : cover (buf_fsm = txt_tx_prog);
-- psl txtb_fsm_ab_prog_cov : cover (buf_fsm = txt_ab_prog);
-- psl txtb_fsm_error_cov : cover (buf_fsm = txt_error);
-- psl txtb_fsm_aborted_cov : cover (buf_fsm = txt_aborted);
-- psl txtb_fsm_tx_ok_cov : cover (buf_fsm = txt_ok);
-- Simultaneous HW and SW Commands
-- psl txtb_rdy_hazard : cover (txt_hw_cmd.lock = '1' and hw_cbs = '1' and
-- txt_sw_cmd.set_abt = '1' and sw_cbs = '1');
-- psl txtb_hw_sw_cmd_hazard_cov : cover
-- (txt_hw_cmd.lock = '1' and hw_cbs = '1' and
-- txt_sw_cmd.set_abt = '1' and sw_cbs = '1');
end block;
----------------------------------------------------------------------------
-- Assertions
----------------------------------------------------------------------------
-- HW Lock command should never arrive when the buffer is in other state
-- than ready
--
-- psl txtb_lock_only_in_rdy_asrt : assert always
-- ((txt_hw_cmd.lock = '1' and hw_cbs = '1') -> buf_fsm = txt_ready)
-- report "TXT Buffer " & integer'image(ID) &
-- " not READY when LOCK command occurred!" severity error;
----------------------------------------------------------------------------
-- HW Unlock command is valid only when Buffer is TX in Progress or Abort in
-- progress.
--
-- psl txtb_unlock_only_in_tx_prog_asrt : assert always
-- ((txt_hw_cmd.unlock = '1' and hw_cbs = '1') ->
-- (buf_fsm = txt_tx_prog or buf_fsm = txt_ab_prog))
-- report "TXT Buffer " & integer'image(ID) &
-- " not READY when LOCK command occurred!" severity error;
----------------------------------------------------------------------------
-- HW Lock command should never occur when there was abort in previous cycle!
--
-- psl txtb_no_lock_after_abort : assert never
-- {abort_applied = '1';txt_hw_cmd.lock = '1' and hw_cbs = '1'}
-- report "LOCK command after ABORT was applied!" severity error;
----------------------------------------------------------------------------
end architecture;
......@@ -151,7 +151,8 @@ begin
bus_sampling_comp : bus_sampling
GENERIC map(
use_Sync => true
use_Sync => true,
reset_polarity => '0'
)
PORT map(
clk_sys => clk_sys,
......
......@@ -404,6 +404,7 @@ begin
-- Selected buffer has changed
elsif (high_prio_buf_index /= high_prio_buf_index_d) then
mod_frame_com <= '0';
del_counter <= 1;
wait until rising_edge(clk_sys);
......