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......@@ -130,8 +130,7 @@ union ctu_can_fd_mode_settings {
uint32_t stm : 1;
uint32_t afm : 1;
uint32_t fde : 1;
uint32_t reserved_5 : 1;
uint32_t tsm : 1;
uint32_t reserved_6_5 : 2;
uint32_t acf : 1;
uint32_t reserved_15_8 : 8;
/* SETTINGS */
......@@ -150,8 +149,7 @@ union ctu_can_fd_mode_settings {
uint32_t rtrle : 1;
uint32_t reserved_15_8 : 8;
uint32_t acf : 1;
uint32_t tsm : 1;
uint32_t reserved_5 : 1;
uint32_t reserved_6_5 : 2;
uint32_t fde : 1;
uint32_t afm : 1;
uint32_t stm : 1;
......@@ -181,11 +179,6 @@ enum ctu_can_fd_mode_fde {
FDE_ENABLE = 0x1,
};
enum ctu_can_fd_mode_tsm {
TSM_DISABLE = 0x0,
TSM_ENABLE = 0x1,
};
enum ctu_can_fd_mode_acf {
ACF_DISABLED = 0x0,
ACF_ENABLED = 0x1,
......
********************************************************************************
** Generating Lyx docs for VHDL entity interfaces!
********************************************************************************
Python version is: python3.6
********************************************************************************
Processing prescaler entity
********************************************************************************
../doc/template.lyx
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template: "../doc/core/template.lyx"
source_list:
bus_sampling:
vhdl_file: "../src/bus_sampling/bus_sampling.vhd"
lyx_output: "../doc/core/entity_docs/bus_sampling.lyx"
fault_confinement:
vhdl_file: "../src/can_core/fault_confinement/fault_confinement.vhd"
lyx_output: "../doc/core/entity_docs/fault_confinement.lyx"
protocol_control:
vhdl_file: "../src/can_core/protocol_control/protocol_control.vhd"
lyx_output: "../doc/core/entity_docs/protocol_control.lyx"
protocol_control_fsm:
vhdl_file: "../src/can_core/protocol_control/protocol_control_fsm.vhd"
lyx_output: "../doc/core/entity_docs/protocol_control_fsm.lyx"
can_core:
vhdl_file: "../src/can_core/can_core.vhd"
lyx_output: "../doc/core/entity_docs/can_core.lyx"
can_top_level:
vhdl_file: "../src/can_top_level.vhd"
lyx_output: "../doc/core/entity_docs/can_top_level.lyx"
operation_control:
vhdl_file: "../src/can_core/operation_control/operation_control.vhd"
lyx_output: "../doc/core/entity_docs/operation_control.lyx"
bit_stuffing:
vhdl_file: "../src/can_core/bit_stuffing/bit_stuffing.vhd"
lyx_output: "../doc/core/entity_docs/bit_stuffing.lyx"
bit_destuffing:
vhdl_file: "../src/can_core/bit_destuffing/bit_destuffing.vhd"
lyx_output: "../doc/core/entity_docs/bit_destuffing.lyx"
can_crc:
vhdl_file: "../src/can_core/crc/can_crc.vhd"
lyx_output: "../doc/core/entity_docs/can_crc.lyx"
prescaler:
vhdl_file: "../src/prescaler/prescaler.vhd"
lyx_output: "../doc/core/entity_docs/prescaler.lyx"
frame_filters:
vhdl_file: "../src/frame_filters/frame_filters.vhd"
lyx_output: "../doc/core/entity_docs/frame_filters.lyx"
memory_registers:
vhdl_file: "../src/memory_registers/memory_registers.vhd"
lyx_output: "../doc/core/entity_docs/memory_registers.lyx"
rx_buffer:
vhdl_file: "../src/rx_buffer/rx_buffer.vhd"
lyx_output: "../doc/core/entity_docs/rx_buffer.lyx"
txt_buffer:
vhdl_file: "../src/txt_buffer/txt_buffer.vhd"
lyx_output: "../doc/core/entity_docs/txt_buffer.lyx"
tx_arbitrator:
vhdl_file: "../src/tx_arbitrator/tx_arbitrator.vhd"
lyx_output: "../doc/core/entity_docs/tx_arbitrator.lyx"
int_manager:
vhdl_file: "../src/interrupts/int_manager.vhd"
lyx_output: "../doc/core/entity_docs/int_manager.lyx"
......@@ -97,32 +97,6 @@
</ipxact:enumeratedValue>
</ipxact:enumeratedValues>
</ipxact:field>
<ipxact:field>
<ipxact:name>TSM</ipxact:name>
<ipxact:displayName>TSM</ipxact:displayName>
<ipxact:description>Tripple sampling mode. Bus value is sampled three times when this mode is enabled. Even if this bit is set, triple sampling is used only during Nominal data rate. CAN standard reccomends to use tripple sampling at low Bit rates.</ipxact:description>
<ipxact:bitOffset>6</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:enumeratedValues>
<ipxact:enumeratedValue>
<ipxact:name>TSM_ENABLE</ipxact:name>
<ipxact:displayName>TSM_ENABLE</ipxact:displayName>
<ipxact:description>Tripple sampling mode enabled</ipxact:description>
<ipxact:value>1</ipxact:value>
</ipxact:enumeratedValue>
<ipxact:enumeratedValue>
<ipxact:name>TSM_DISABLE</ipxact:name>
<ipxact:displayName>TSM_DISABLE</ipxact:displayName>
<ipxact:description>Tripple sampling mode disabled</ipxact:description>
<ipxact:value>0</ipxact:value>
</ipxact:enumeratedValue>
</ipxact:enumeratedValues>
</ipxact:field>
<ipxact:field>
<ipxact:name>ACF</ipxact:name>
<ipxact:displayName>ACF</ipxact:displayName>
......
......@@ -101,11 +101,8 @@ entity bit_error_detector is
-- Delayed transmitted data (for detection in secondary sampling point)
data_tx_delayed :in std_logic;
-- Receieved data in Nominal Bit time
data_rx_nbt :in std_logic;
-- Received data (both Nominal Bit time and Data Bit time)
can_rx_i :in std_logic;
-- RX Data (Synchronised)
data_rx_synced :in std_logic;
-----------------------------------------------------------------------
-- Status outputs
......@@ -122,9 +119,6 @@ architecture rtl of bit_error_detector is
-- Expected bit value (TX, from SYNC)
signal exp_data : std_logic;
-- Actual data value (RX, from Sample point)
signal act_data : std_logic;
-- Bit error detected value
signal bit_error_d : std_logic;
......@@ -143,20 +137,14 @@ begin
----------------------------------------------------------------------------
exp_data <= data_tx_delayed when (sp_control = SECONDARY_SAMPLE) else
data_tx;
----------------------------------------------------------------------------
-- Actual data. Consider tripple sampling for Nominal Bit-rate
----------------------------------------------------------------------------
act_data <= data_rx_nbt when (sp_control = NOMINAL_SAMPLE) else
can_rx_i;
----------------------------------------------------------------------------
-- Bit Error detection. If expected data is not equal to actual data in
-- sample point -> Bit Error!
----------------------------------------------------------------------------
bit_error_d <= '0' when (drv_ena = CTU_CAN_DISABLED) else
'1' when (exp_data /= act_data and sample = '1') else
'0' when (exp_data = act_data and sample = '1') else
'1' when (exp_data /= data_rx_synced and sample = '1') else
'0' when (exp_data = data_rx_synced and sample = '1') else
bit_error_q;
----------------------------------------------------------------------------
......
......@@ -203,9 +203,6 @@ architecture rtl of bus_sampling is
-- Driving bus aliases
-----------------------------------------------------------------------------
-- Tripple sampling (as SJA1000)
signal drv_sam : std_logic;
-- Enable of the whole driver
signal drv_ena : std_logic;
......@@ -219,21 +216,8 @@ architecture rtl of bus_sampling is
-----------------------------------------------------------------------------
-- Internal registers and signals
-----------------------------------------------------------------------------
-- CAN RX synchronisation chain output
signal can_rx_synced : std_logic;
-- Internal received CAN Data. Selected between Raw input value and
-- synchronised value by signal synchroniser.
signal can_rx_i : std_logic;
-- Majority value from all three sampled values in tripple sampling shift
-- register
signal can_rx_trs_majority : std_logic;
-- CAN RX Data selected between normally sampled data (can_rx_i) and
-- Tripple sampled data!
signal data_rx_nbt : std_logic;
-- CAN RX Data (Synchronised)
signal data_rx_synced : std_logic;
-- Bus sampling and edge detection, Previously sampled value on CAN bus
signal prev_Sample : std_logic;
......@@ -284,7 +268,6 @@ begin
---------------------------------------------------------------------------
-- Driving bus aliases
---------------------------------------------------------------------------
drv_sam <= drv_bus(DRV_SAM_INDEX);
drv_ena <= drv_bus(DRV_ENA_INDEX);
drv_ssp_offset <= drv_bus(DRV_SSP_OFFSET_HIGH downto
......@@ -304,13 +287,8 @@ begin
res_n => res_n,
clk => clk_sys,
async => can_rx,
sync => can_rx_synced
sync => data_rx_synced
);
---------------------------------------------------------------------------
-- Synchronisation-chain selection
---------------------------------------------------------------------------
can_rx_i <= can_rx_synced;
---------------------------------------------------------------------------
-- Component for measurement of transceiver delay and calculation of
......@@ -348,17 +326,6 @@ begin
trv_delay(trv_delay_i'length - 1 downto 0) <= trv_delay_i;
---------------------------------------------------------------------------
-- Tripple sampling majority selection
---------------------------------------------------------------------------
trs_maj_dec_inst : majority_decoder_3
port map(
input => trs_reg, -- IN
output => can_rx_trs_majority -- OUT
);
---------------------------------------------------------------------------
-- Edge detector on TX, RX Data
---------------------------------------------------------------------------
......@@ -370,7 +337,7 @@ begin
clk_sys => clk_sys, -- IN
res_n => res_n, -- IN
tx_data => tx_data_wbs, -- IN
rx_data => can_rx_i, -- IN
rx_data => data_rx_synced, -- IN
prev_rx_sample => prev_sample, -- IN
tx_edge => edge_tx_valid, -- OUT
......@@ -401,7 +368,7 @@ begin
clk => clk_sys, -- IN
input => shift_regs_res_d, -- IN
load => '0', -- IN
load => '1', -- IN
output => shift_regs_res_q -- OUT
);
......@@ -456,7 +423,7 @@ begin
clk_sys => clk_sys, -- IN
res_n => shift_regs_res_q, -- IN
write => rx_trigger, -- IN
read => sample_sec, -- IN
read => sample_sec_i, -- IN
data_in => tx_data_wbs, -- IN
data_out => data_tx_delayed -- OUT
......@@ -469,7 +436,7 @@ begin
ssp_gen_proc : process(res_n, clk_sys)
begin
if (res_n = G_RESET_POLARITY) then
sample_sec <= '0';
sample_sec_i <= '0';
elsif rising_edge(clk_sys) then
if (ssp_reset = '1') then
......@@ -481,40 +448,6 @@ begin
end process;
----------------------------------------------------------------------------
-- Separate process for tripple sampling with simple shift register.
-- Sampling is continous into shift register of lenth 3. If this option is
-- desired then majority out of whole shift register is selected as sampled
-- value!
----------------------------------------------------------------------------
trs_shift_reg_inst : shift_reg_preload
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RESET_VALUE => "000",
G_WIDTH => 3,
G_SHIFT_DOWN => false
)
port map(
clk => clk_sys, -- IN
res_n => res_n, -- IN
input => can_rx_i, -- IN
preload => '0', -- IN
preload_val => "000", -- IN
enable => '1', -- IN
reg_stat => trs_reg, -- OUT
output => open -- OUT
);
---------------------------------------------------------------------------
-- Selection of RX Data sampled in Nominal Bit-rate between Normally
-- sampled and tripple sampled data.
---------------------------------------------------------------------------
data_rx_nbt <= can_rx_trs_majority when (drv_sam = TSM_ENABLE) else
can_rx_i;
---------------------------------------------------------------------------
-- Bit error detector
---------------------------------------------------------------------------
......@@ -531,8 +464,7 @@ begin
sample_sec => sample_sec_i, -- IN
data_tx => tx_data_wbs, -- IN
data_tx_delayed => data_tx_delayed, -- IN
data_rx_nbt => data_rx_nbt, -- IN
can_rx_i => can_rx_i, -- IN
data_rx_synced => data_rx_synced, -- IN
bit_error => bit_Error -- OUT
);
......@@ -551,8 +483,7 @@ begin
sp_control => sp_control, -- IN
rx_trigger => rx_trigger, -- IN
sample_sec => sample_sec_i, -- IN
data_rx_nbt => data_rx_nbt, -- IN
can_rx_i => can_rx_i, -- IN
data_rx_synced => data_rx_synced, -- IN
prev_sample => prev_sample, -- OUT
data_rx => rx_data_wbs -- OUT
......
......@@ -95,11 +95,8 @@ entity sample_mux is
-----------------------------------------------------------------------
-- Datapath
-----------------------------------------------------------------------
-- Receieved data in Nominal Bit time
data_rx_nbt :in std_logic;
-- Received data (Nominal Bit Time and Data Bit Time)
can_rx_i :in std_logic;
-- RX Data (synchronised)
data_rx_synced :in std_logic;
-- Sampled value of RX pin in Sample point (DFF output)
prev_sample :out std_logic;
......@@ -113,9 +110,6 @@ architecture rtl of sample_mux is
-- Internal sample signal (muxed for NBT, DBT and SAMPLE)
signal sample : std_logic;
-- RX Data
signal rx_data_i : std_logic;
-- Bit error detected value
signal sample_prev_d : std_logic;
......@@ -129,16 +123,10 @@ begin
sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else
rx_trigger;
----------------------------------------------------------------------------
-- RX data mux.
----------------------------------------------------------------------------
rx_data_i <= data_rx_nbt when (sp_control = NOMINAL_SAMPLE) else
can_rx_i;
----------------------------------------------------------------------------
-- Previous sample register
----------------------------------------------------------------------------
sample_prev_d <= rx_data_i when (sample = '1') else
sample_prev_d <= data_rx_synced when (sample = '1') else
sample_prev_q;
sample_prev_req_proc : process(clk_sys, res_n)
......@@ -155,7 +143,7 @@ begin
----------------------------------------------------------------------------
-- Internal signal to output propagation
----------------------------------------------------------------------------
rx_data_i <= rx_data_i;
data_rx <= data_rx_synced;
-- Internal signal to output propagation
prev_sample <= sample_prev_q;
......
......@@ -262,7 +262,7 @@ begin
----------------------------------------------------------------------------
-- Register for transceiver delay measurement progress flag.
----------------------------------------------------------------------------
trv_del_ctr_proc : process(res_n, clk_sys)
trv_del_ctr_proc : process(res_n, clk_sys, trv_delay_ctr_rst)
begin
if (res_n = G_RESET_POLARITY or trv_delay_ctr_rst = '1') then
trv_delay_ctr_reg <= (OTHERS => '0');
......
......@@ -140,7 +140,7 @@ begin
----------------------------------------------------------------------------
-- TX Counter register
----------------------------------------------------------------------------
tx_ctr_proc : process(clk_sys, res_n)
tx_ctr_proc : process(clk_sys, res_n, clear_tx_ctr)
begin
if (res_n = G_RESET_POLARITY or clear_tx_ctr = '1') then
tx_ctr_int <= (OTHERS => '0');
......@@ -156,7 +156,7 @@ begin
----------------------------------------------------------------------------
-- RX Counter register
----------------------------------------------------------------------------
rx_ctr_proc : process(clk_sys, res_n)
rx_ctr_proc : process(clk_sys, res_n, clear_rx_ctr)
begin
if (res_n = G_RESET_POLARITY or clear_rx_ctr = '1') then
rx_ctr_int <= (OTHERS => '0');
......
......@@ -275,12 +275,6 @@ architecture rtl of can_core is
----------------------------------------------------------------------------
-- TXT Buffer control
signal tran_word_i : std_logic_vector(31 downto 0);
signal tran_dlc_i : std_logic_vector(3 downto 0);
signal tran_is_rtr_i : std_logic;
signal tran_ident_type_i : std_logic;
signal tran_frame_type_i : std_logic;
signal tran_brs_i : std_logic;
signal txtb_hw_cmd_i : t_txtb_hw_cmd;
-- Received frame
......@@ -461,12 +455,12 @@ begin
is_overload => is_overload, -- OUT
-- TXT Buffers interface
tran_word => tran_word_i, -- IN
tran_dlc => tran_dlc_i, -- IN
tran_is_rtr => tran_is_rtr_i, -- IN
tran_ident_type => tran_ident_type_i, -- IN
tran_frame_type => tran_frame_type_i, -- IN
tran_brs => tran_brs_i, -- IN
tran_word => tran_word, -- IN
tran_dlc => tran_dlc, -- IN
tran_is_rtr => tran_is_rtr, -- IN
tran_ident_type => tran_ident_type, -- IN
tran_frame_type => tran_frame_type, -- IN
tran_brs => tran_brs, -- IN
tran_frame_valid => tran_frame_valid, -- IN
txtb_hw_cmd => txtb_hw_cmd_i, -- IN
txtb_ptr => txtb_ptr, -- OUT
......@@ -878,7 +872,6 @@ begin
-- 2. RX Data before Bit destuffing.
---------------------------------------------------------------------------
crc_data_tx_wbs <= bst_data_out;
crc_data_rx_wbs <= bds_data_in;
lpb_dominant <= rx_data_wbs and bst_data_out;
......
......@@ -126,6 +126,9 @@ architecture rtl of fault_confinement_fsm is
signal tx_err_ctr_mt_erp : std_logic;
signal rx_err_ctr_mt_erp : std_logic;
signal tx_err_ctr_mt_ewl : std_logic;
signal rx_err_ctr_mt_ewl : std_logic;
signal tx_err_ctr_mt_255 : std_logic;
......@@ -137,18 +140,30 @@ architecture rtl of fault_confinement_fsm is
begin
-- TX Error counter more than Error warning limit
-- TX Error counter more than Error Passive Limit
tx_err_ctr_mt_erp <= '1' when (unsigned(tx_err_ctr) > unsigned(erp)) else
'0';
-- RX Error counter more than Error warning limit
-- RX Error counter more than Error Passive Limit
rx_err_ctr_mt_erp <= '1' when (unsigned(rx_err_ctr) > unsigned(erp)) else
'0';
-- TX Error counter more than 255
tx_err_ctr_mt_255 <= '1' when (unsigned(tx_err_ctr) > 255) else
'0';
-- TX Error counter more than Error Passive Limit
tx_err_ctr_mt_ewl <= '1' when (unsigned(tx_err_ctr) > unsigned(ewl)) else
'0';
-- RX Error counter more than Error Passive Limit
rx_err_ctr_mt_ewl <= '1' when (unsigned(rx_err_ctr) > unsigned(ewl)) else
'0';
error_warning_limit <= '1' when (tx_err_ctr_mt_ewl = '1' or
rx_err_ctr_mt_ewl = '1')
else
'0';
---------------------------------------------------------------------------
-- Next state process
......
......@@ -137,7 +137,7 @@ begin
-- Next state
---------------------------------------------------------------------------
next_state_proc : process(curr_state, set_idle, set_transmitter,
set_receiver, arbitration_lost)
set_receiver, arbitration_lost, drv_ena)
begin
next_state <= curr_state;
......
......@@ -793,7 +793,8 @@ begin
curr_state, drv_ena, err_frm_req, ctrl_ctr_zero, no_data_field,
drv_fd_type, allow_2bit_crc_delim, allow_2bit_ack, is_receiver,
is_bus_off, go_to_suspend, tx_frame_ready, drv_bus_off_reset,
reinteg_ctr_expired, rx_data)
reinteg_ctr_expired, rx_data, is_err_active, go_to_stuff_count
)
begin
next_state <= curr_state;
......@@ -1162,7 +1163,9 @@ begin
drv_fd_type, ctrl_counted_byte, ctrl_counted_byte_index, is_fd_frame,
is_receiver, crc_match, drv_ack_forb, drv_self_test_ena, tx_frame_ready,
go_to_suspend, frame_start, ctrl_ctr_one, drv_bus_off_reset,
reinteg_ctr_expired, first_err_delim_q)
reinteg_ctr_expired, first_err_delim_q, go_to_stuff_count,
crc_length_i, data_length_bits_c, ctrl_ctr_mem_index
)
begin
-----------------------------------------------------------------------
......@@ -2500,7 +2503,6 @@ begin
stuff_enable <= '1';
elsif (stuff_enable_clear = '1') then
stuff_enable <= '0';
stuff_error_enable <= '0';
end if;
end if;
end process;
......@@ -2569,6 +2571,7 @@ begin
rx_clear <= rx_clear_q;
sync_control <= sync_control_q;
txtb_ptr <= txtb_ptr_q;
pc_state <= curr_state;
bit_error_enable <= not bit_err_disable;
......
......@@ -88,9 +88,6 @@ entity rx_shift_reg is
-----------------------------------------------------------------------
-- Data-path interface
-----------------------------------------------------------------------
-- Actual TX Data
tx_data :out std_logic;
-- Actual RX Data
rx_data :in std_logic;
......
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