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Commits (5)
Subproject commit 210cc07c4b2b9948bafbec6e2b03b0257c70e8de
Subproject commit aa2bb9d95d64cd48b6d7d3d2c219082b753e34c8
......@@ -449,8 +449,7 @@ begin
-- 2. Set to RECESSIVE when non-fixed bit stuffing changes to fixed
-- bit stuffing. TODO: IS THIS OK???
---------------------------------------------------------------------------
prev_val_d <= RECESSIVE when (destuff_enable = '1' and enable_prev = '0') else
RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
data_in when (bds_trigger = '1') else
prev_val_q;
......
......@@ -408,8 +408,7 @@ begin
-- 3. Pipe the input data upon trigger without stufffing
-- 4. Keep previous value otherwise
---------------------------------------------------------------------------
data_out_nxt_ena <= RECESSIVE when (enable_prev = '0') else
(not data_out_int) when (bst_trigger = '1' and insert_stuff_bit = '1') else
data_out_nxt_ena <= (not data_out_int) when (bst_trigger = '1' and insert_stuff_bit = '1') else
data_in when (bst_trigger = '1') else
data_out_int;
......
......@@ -311,6 +311,9 @@ architecture rtl of resynchronisation is
-- SJW more than 0
signal sjw_mt_zero : std_logic;
-- Choose basic segment length
signal use_basic_segm_length : std_logic;
begin
......@@ -329,6 +332,7 @@ begin
resize(unsigned(tseg_2), C_BS_WIDTH);
segm_extension <=
to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1') else
resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else
resize(unsigned(bt_counter), C_EXT_WIDTH);
......@@ -338,19 +342,37 @@ begin
segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) -
resize(segm_extension, C_EXP_WIDTH);
sync_segm_length <= segm_ext_sub when (is_tseg2 = '1') else
sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1')
else
segm_ext_add;
---------------------------------------------------------------------------
-- Use basic segment length:
-- 1. Circuit start
-- 2. Segment end, but not due to hard-sync. When segment end due to hard
-- sync occurs, we must take TSEG1 - 1 which is calculated in synced
-- segment length!
---------------------------------------------------------------------------
use_basic_segm_length <= '1' when (start_edge = '1')
else
'1' when (segm_end = '1' and
h_sync_valid = '0')
else
'0';
---------------------------------------------------------------------------
-- Expected length of segment register. Load:
-- 1. Nominal length of next segment
-- 2. Value post-resynchronisation.
-- 2. Value post-synchronisation.
---------------------------------------------------------------------------
exp_seg_length_d <=
resize(basic_segm_length, C_EXP_WIDTH) when (segm_end = '1' or start_edge = '1') else
resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')
else
resize(sync_segm_length, C_EXP_WIDTH);
exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or
exp_seg_length_ce <= '1' when (segm_end = '1' or
resync_edge_valid = '1' or
h_sync_valid = '1' or
start_edge = '1')
else
'0';
......
......@@ -249,7 +249,6 @@ architecture func of prescaler_model is
begin
exp_duration <= nom_dur;
i <= 0;
wait for 0 ns;
while (i < exp_duration) loop
......@@ -493,6 +492,17 @@ begin
bt_fsm_i <= s_bt_tseg1;
-------------------------------------------------------------------
-- If Hard synchronisation occured and we are here, TSEG1 must
-- start from 1, not zero, since we skip SYNC segment!
-------------------------------------------------------------------
if (h_sync_occured_tseg1.get) then
tseg1_i <= 1;
else
tseg1_i <= 0;
end if;
wait for 0 ns;
-- Execute segment 1
count_segment (
clk_sys => clk_sys,
......@@ -568,6 +578,8 @@ begin
if (drv_ena = '1') then
wait until tseg2_nbt_req = true;
tseg2_nbt_ack <= false;
tseg2_nbt_i <= 0;
wait for 0 ns;
count_segment (
clk_sys => clk_sys,
......@@ -584,7 +596,7 @@ begin
h_sync_occured => h_sync_occured_tseg2_nbt,
edge_occured => edge_occured_tseg2_nbt
);
if (drv_ena = '1' and sp_control = NOMINAL_SAMPLE) then
tseg2_nbt_ack <= true;
end if;
......@@ -610,6 +622,8 @@ begin
if (drv_ena = '1') then
wait until tseg2_dbt_req = true;
tseg2_dbt_ack <= false;
tseg2_dbt_i <= 0;
wait for 0 ns;
count_segment (
clk_sys => clk_sys,
......
......@@ -254,6 +254,11 @@ architecture bit_stuffing_unit_test of CAN_test is
-- LCOV_EXCL_STOP
end if;
-- Set previous bit to actual input of Bit stuffing. This corresponds
-- to previously propagated bit value when bit stuffing was not yet
-- enabled!
prev_bit := tx_data;
--------------------------------------
-- Calculate non-fixed stuffing
--------------------------------------
......