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Commits (5)
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......@@ -268,7 +268,7 @@ union ctu_can_fd_int_stat {
uint32_t epi : 1;
uint32_t ali : 1;
uint32_t bei : 1;
uint32_t lfi : 1;
uint32_t reserved_7 : 1;
uint32_t rxfi : 1;
uint32_t bsi : 1;
uint32_t rbnei : 1;
......@@ -280,7 +280,7 @@ union ctu_can_fd_int_stat {
uint32_t rbnei : 1;
uint32_t bsi : 1;
uint32_t rxfi : 1;
uint32_t lfi : 1;
uint32_t reserved_7 : 1;
uint32_t bei : 1;
uint32_t ali : 1;
uint32_t epi : 1;
......
......@@ -607,19 +607,6 @@
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
<ipxact:field>
<ipxact:name>LFI</ipxact:name>
<ipxact:displayName>LFI</ipxact:displayName>
<ipxact:description>Event logging finished interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
<ipxact:field>
<ipxact:name>RXFI</ipxact:name>
<ipxact:displayName>RXFI</ipxact:displayName>
......
......@@ -368,7 +368,6 @@ architecture rtl of can_core is
signal crc_trig_tx_nbs : std_logic;
signal crc_trig_rx_wbs : std_logic;
signal crc_trig_rx_nbs : std_logic;
signal tx_trigger_q : std_logic;
-- Bit stuffing signals
signal bst_data_in : std_logic;
......@@ -740,109 +739,42 @@ begin
---------------------------------------------------------------------------
-- Trigger multiplexor
---------------------------------------------------------------------------
-- Trigger signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Protocol control triggers:
-- 1. TX Trigger which shifts TX Shift register is enabled when
-- stuff bit is not inserted!
-- 2. RX Trigger which shifts RX Shift register is enabled when
-- stuff bit is not destuffed!
---------------------------------------------------------------------------
pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0')
else
'0';
pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0')
else
'0';
---------------------------------------------------------------------------
-- Bit stuffing/destuffing triggers:
-- 1. Bit Stuffing - TX Trigger, stuff bit does not make any change here
-- since also stuff bit must be processed by Bit Stuffing.
-- 2. Bit Destuffing - RX Trigger, one clock cycle in advance of TX
-- Trigger for protocol control, since Bit stuffing is pipelined!
-- Destuffed bits shall not block bit destuffing since these must also
-- be processed by Bit destuffing.
---------------------------------------------------------------------------
bst_trigger <= tx_trigger;
bds_trigger <= rx_triggers(1);
---------------------------------------------------------------------------
-- CRC Triggers for CRC 15 (no bit stuffing):
-- 1. CRC RX NBS - Trigger for CRC15 from RX data without bit stuffing.
-- The same trigger as for Protocol control reception in sample point.
-- Trigger must be gated when bit was destuffed, because CRC15 for
-- CAN 2.0 frames shall not take stuff bits into account!
-- 2. CRC TX NBS - Trigger for CRC15 from TX data without bit stuffing.
-- The same trigger as TX Trigger (inserts stuff bit). Must be gated
-- when stuff bit is inserted!
---------------------------------------------------------------------------
crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0')
else
'0';
crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0')
else
'0';
---------------------------------------------------------------------------
-- CRC Trigger for CRC 17, 21 (with bit stuffing):
-- 1. CRC TX WBS - Trigger for CRC17, CRC21 from TX Data with bit stuffing.
-- Trigger one clock cycle delayed from TX Trigger. Note that this
-- trigger may be delayed since resynchronisation will never shorten
-- phase 1 (between TX and RX triggers). This trigger must be gated
-- for fixed stuff bits!!
-- 2. CRC RX WBS Trigger is the same trigger as the one used to process
-- data by bit destuffing (one clock cycle in advance of Protocol
-- control sampling)! Fixed stuff bits must be left out!
---------------------------------------------------------------------------
crc_trig_tx_wbs_reg : dff_arst
trigger_mux_inst : trigger_mux
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_SAMPLE_TRIGGER_COUNT => G_SAMPLE_TRIGGER_COUNT
)
port map(
arst => res_n,
clk => clk_sys,
-- Clock and Asynchronous reset
clk_sys => clk_sys,
res_n => res_n,
-- Input triggers
rx_triggers => rx_triggers,
tx_trigger => tx_trigger,
input => tx_trigger,
ce => '1',
output => tx_trigger_q
-- Control signals
data_halt => data_halt,
destuffed => destuffed,
fixed_stuff => fixed_stuff,
bds_data_in => bds_data_in,
-- Output triggers
pc_tx_trigger => pc_tx_trigger,
pc_rx_trigger => pc_rx_trigger,
bst_trigger => bst_trigger,
bds_trigger => bds_trigger,
crc_trig_rx_nbs => crc_trig_rx_nbs,
crc_trig_tx_nbs => crc_trig_tx_nbs,
crc_trig_rx_wbs => crc_trig_rx_wbs,
crc_trig_tx_wbs => crc_trig_tx_wbs,
-- Status signals
crc_data_rx_wbs => crc_data_rx_wbs
);
crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else
'1' when (tx_trigger_q = '1') else
'0';
---------------------------------------------------------------------------
-- We must gate fixed stuff bit for CRC from RX With Bit Stuffing. But we
-- don't know if it is stuff bit, because this should be calculated at the
-- same clock cycle as bit destuffing! So we must belay the information
-- here! We sample the data (Bit Destuffing input) to avoid possible change,
-- and calculate the CRC with rx_trigger(0) (the same trigger as sample
-- point).
---------------------------------------------------------------------------
crc_data_rx_wbs_reg : dff_arst
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
clk => clk_sys,
input => bds_data_in,
ce => rx_triggers(1),
output => crc_data_rx_wbs
);
crc_trig_rx_wbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') else
'0';
---------------------------------------------------------------------------
---------------------------------------------------------------------------
......
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......@@ -162,7 +162,7 @@ entity int_manager is
-- Interrupt enable
int_ena :out std_logic_vector(G_INT_COUNT - 1 downto 0)
);
);
end entity;
architecture rtl of int_manager is
......@@ -255,6 +255,8 @@ begin
int_input_active(RBNEI_IND) <= not rx_empty;
int_input_active(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int);
-- Logger finished interrupt removed after logger was thrown out!
int_input_active(7) <= '0';
---------------------------------------------------------------------------
-- Interrupt module instances
......@@ -341,13 +343,6 @@ begin
-- (int_vect_i(BEI_IND) = '1' and int_ena(BEI_IND) = '1');
-- psl lfi_int_set_cov : cover
-- {int_vect_i(LFI_IND) = '0';int_vect_i(LFI_IND) = '1'};
-- psl lfi_enable_cov : cover
-- (int_vect_i(LFI_IND) = '1' and int_ena(LFI_IND) = '1');
-- psl rxfi_int_set_cov : cover
-- {int_vect_i(RXFI_IND) = '0';int_vect_i(RXFI_IND) = '1'};
......
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......@@ -624,7 +624,6 @@ package can_fd_register_map is
constant EPI_IND : natural := 4;
constant ALI_IND : natural := 5;
constant BEI_IND : natural := 6;
constant LFI_IND : natural := 7;
constant RXFI_IND : natural := 8;
constant BSI_IND : natural := 9;
constant RBNEI_IND : natural := 10;
......@@ -638,7 +637,6 @@ package can_fd_register_map is
constant EPI_RSTVAL : std_logic := '0';
constant ALI_RSTVAL : std_logic := '0';
constant BEI_RSTVAL : std_logic := '0';
constant LFI_RSTVAL : std_logic := '0';
constant RXFI_RSTVAL : std_logic := '0';
constant BSI_RSTVAL : std_logic := '0';
constant RBNEI_RSTVAL : std_logic := '0';
......
......@@ -182,10 +182,10 @@ begin
int_stat_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111111111111" ,
data_mask => "0000111101111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111"
auto_clear => "0000111101111111"
)
port map(
clk_sys => clk_sys ,-- in
......
......@@ -876,24 +876,24 @@ begin
----------------------------------------------------------------------------
-- RAM Memory of RX Buffer
----------------------------------------------------------------------------
rx_buf_RAM_inst : inf_RAM_wrapper
generic map (
G_WORD_WIDTH => 32,
G_DEPTH => G_RX_BUFF_SIZE,
G_ADDRESS_WIDTH => RAM_write_address'length,
G_RESET_POLARITY => G_RESET_POLARITY,
G_SIMULATION_RESET => true,
G_SYNC_READ => true
rx_buffer_ram_inst : rx_buffer_ram
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RX_BUFF_SIZE => G_RX_BUFF_SIZE
)
port map(
clk_sys => clk_sys, -- IN
res_n => rx_buf_res_q, -- IN
addr_A => RAM_write_address, -- IN
write => RAM_write, -- IN
data_in => memory_write_data, -- IN
addr_B => RAM_read_address, -- IN
data_out => RAM_data_out -- OUT
-- Clocks and Asynchronous reset
clk_sys => clk_sys,
res_n => res_n,
-- Port A - Write (from CAN Core)
port_a_address => RAM_write_address,
port_a_data_in => memory_write_data,
port_a_write => RAM_write,
-- Port B - Read (from Memory registers)
port_b_address => RAM_read_address,
port_b_data_out => RAM_data_out
);
-- Memory written either on regular write or Extra timestamp write
......
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......@@ -4099,10 +4099,6 @@ package body CANtestLib is
tmp(BEI_IND) := '1';
end if;
if (interrupts.logger_finished_int) then
tmp(LFI_IND) := '1';
end if;
if (interrupts.rx_buffer_full_int) then
tmp(RXFI_IND) := '1';
end if;
......@@ -4159,10 +4155,6 @@ package body CANtestLib is
tmp.bus_error_int := true;
end if;
if (int_reg(LFI_IND) = '1') then
tmp.logger_finished_int := true;
end if;
if (int_reg(RXFI_IND) = '1') then
tmp.rx_buffer_full_int := true;
end if;
......