...
 
Commits (10)
......@@ -743,7 +743,7 @@ Frame format word with CAN frame metadata.
\align center
\begin_inset Tabular
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<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
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......@@ -1063,7 +1063,7 @@ cellcolor{cyan}
\align center
\begin_inset Tabular
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<features islongtable="true" longtabularalignment="center">
<features>
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<column alignment="center" valignment="top" width="1.4cm">
......@@ -1383,7 +1383,7 @@ cellcolor{cyan}
\align center
\begin_inset Tabular
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<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -1703,7 +1703,7 @@ X\end_layout
\align center
\begin_inset Tabular
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<features islongtable="true" longtabularalignment="center">
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......@@ -2085,7 +2085,7 @@ CAN Identifier
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
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......@@ -2405,7 +2405,7 @@ X\end_layout
\align center
\begin_inset Tabular
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<features islongtable="true" longtabularalignment="center">
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......@@ -2725,7 +2725,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -3045,7 +3045,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -3397,7 +3397,7 @@ Size: 4 bytes
\align center
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<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -3717,7 +3717,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
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......@@ -4037,7 +4037,7 @@ X\end_layout
\align center
\begin_inset Tabular
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<features islongtable="true" longtabularalignment="center">
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......@@ -4357,7 +4357,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -4706,7 +4706,7 @@ Size: 4 bytes
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -5026,7 +5026,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -5346,7 +5346,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -5666,7 +5666,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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......@@ -6015,7 +6015,7 @@ Size: 4 bytes
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
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......@@ -6335,7 +6335,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
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......@@ -6655,7 +6655,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
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......@@ -6975,7 +6975,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
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......@@ -7333,7 +7333,7 @@ Size: 4 bytes
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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<column alignment="center" valignment="top" width="1.4cm">
......@@ -7653,7 +7653,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
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<column alignment="center" valignment="top" width="1.4cm">
......@@ -7973,7 +7973,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
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<column alignment="center" valignment="top" width="1.4cm">
......@@ -8293,7 +8293,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
<column alignment="center" valignment="top" width="1.4cm">
<column alignment="center" valignment="top" width="1.4cm">
......@@ -8651,7 +8651,7 @@ Size: 4 bytes
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
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<column alignment="center" valignment="top" width="1.4cm">
......@@ -8971,7 +8971,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
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<column alignment="center" valignment="top" width="1.4cm">
......@@ -9291,7 +9291,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
<column alignment="center" valignment="top" width="1.4cm">
<column alignment="center" valignment="top" width="1.4cm">
......@@ -9611,7 +9611,7 @@ X\end_layout
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features islongtable="true" longtabularalignment="center">
<features>
<column alignment="center" valignment="top">
<column alignment="center" valignment="top" width="1.4cm">
<column alignment="center" valignment="top" width="1.4cm">
......
This diff is collapsed.
......@@ -868,8 +868,8 @@ union ctu_can_fd_trv_delay_ssp_cfg {
};
enum ctu_can_fd_ssp_cfg_ssp_src {
SSP_SRC_MEASURED = 0x0,
SSP_SRC_MEAS_N_OFFSET = 0x1,
SSP_SRC_MEAS_N_OFFSET = 0x0,
SSP_SRC_NO_SSP = 0x1,
SSP_SRC_OFFSET = 0x2,
};
......
......@@ -193,7 +193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>bd93fd12</spirit:value>
<spirit:value>87bf052c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -209,7 +209,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>bd93fd12</spirit:value>
<spirit:value>87bf052c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -223,7 +223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>aabbb6d4</spirit:value>
<spirit:value>0743f567</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -486,11 +486,6 @@
<spirit:displayName>Rx Buffer Size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.rx_buffer_size" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">128</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>use_sync</spirit:name>
<spirit:displayName>Use Sync</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.use_sync">true</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>sup_filtA</spirit:name>
<spirit:displayName>Sup Filta</spirit:displayName>
......@@ -559,28 +554,18 @@
<spirit:file>
<spirit:name>xgui/CTU_CAN_FD_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_aabbb6d4</spirit:userFileType>
<spirit:userFileType>CHECKSUM_0743f567</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>CTU_CAN_FD_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>use_logger</spirit:name>
<spirit:displayName>Use Logger</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.use_logger">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>rx_buffer_size</spirit:name>
<spirit:displayName>Rx Buffer Size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.rx_buffer_size" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">128</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>use_sync</spirit:name>
<spirit:displayName>Use Sync</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.use_sync">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sup_filtA</spirit:name>
<spirit:displayName>Sup Filta</spirit:displayName>
......@@ -601,11 +586,6 @@
<spirit:displayName>Sup Range</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.sup_range">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>logger_size</spirit:name>
<spirit:displayName>Logger Size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.logger_size" spirit:minimum="0" spirit:maximum="512" spirit:rangeType="long">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">CTU_CAN_FD_v1_0</spirit:value>
......@@ -623,20 +603,20 @@
</xilinx:taxonomies>
<xilinx:displayName>CTU_CAN_FD_v1_0</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2019-01-07T11:37:47Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>5</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2019-05-27T16:56:46Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
<xilinx:tag xilinx:name="user.org:user:CTU_CAN_FD:1.0_ARCHIVE_LOCATION">/home/pi/fpga/zynq/canbech-sw/modules/CTU_CAN_FD/src</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
<xilinx:xilinxVersion>2018.2.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="c572df2c"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cdef2cce"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4e435b33"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="0d5541f6"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5d342b85"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="72b5e748"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="cddf56a5"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
Subproject commit aa2bb9d95d64cd48b6d7d3d2c219082b753e34c8
Subproject commit 73bd4136dfcc0a7c72aa95b828fb85957fedefc1
......@@ -1411,7 +1411,7 @@
</ipxact:register>
<ipxact:register>
<ipxact:name>SSP_CFG</ipxact:name>
<ipxact:description>Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:description>Configuration of Secondary Sampling Point which is used by Transmitter in Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h82</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -1419,18 +1419,18 @@
<ipxact:access>read-write</ipxact:access>
<ipxact:field>
<ipxact:name>SSP_OFFSET</ipxact:name>
<ipxact:description>Secondary sampling point offset.</ipxact:description>
<ipxact:description>Secondary sampling point offset. Value is given as multiple of Minimal Data Time Quanta.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
<ipxact:value>4</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>7</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>SSP_SRC</ipxact:name>
<ipxact:description>Source of secondary sampling point delay. Measured in clock cycles, not Time quanta! Sampling point is delayed from regular sampling point by a value configured by this register. If configured value exceeds 130, it is saturated on 130. Thus maximal possible delay is 130 clk_sys clock cycles.</ipxact:description>
<ipxact:description>Source of Secondary Sampling Point. If configured value exceeds 130 Minimal Time Quanta, it is saturated to 130. Thus maximal possible delay is 130 minimal Time Quanta.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -1439,22 +1439,22 @@
</ipxact:resets>
<ipxact:bitWidth>2</ipxact:bitWidth>
<ipxact:enumeratedValues>
<ipxact:enumeratedValue>
<ipxact:name>SSP_SRC_MEASURED</ipxact:name>
<ipxact:displayName>TRV_SRC_MEASURED</ipxact:displayName>
<ipxact:description>Use measured value (also available in TRV_DELAY).</ipxact:description>
<ipxact:value>0</ipxact:value>
</ipxact:enumeratedValue>
<ipxact:enumeratedValue>
<ipxact:name>SSP_SRC_OFFSET</ipxact:name>
<ipxact:displayName>TRV_SRC_OFFSET</ipxact:displayName>
<ipxact:description>Use SSP_OFFSET value.</ipxact:description>
<ipxact:displayName>SSP_SRC_OFFSET</ipxact:displayName>
<ipxact:description>SSP position = SSP_Offset. Measured value is ignored.</ipxact:description>
<ipxact:value>2</ipxact:value>
</ipxact:enumeratedValue>
<ipxact:enumeratedValue>
<ipxact:name>SSP_SRC_MEAS_N_OFFSET</ipxact:name>
<ipxact:displayName>TRV_SRC_MEAS_N_OFFSET</ipxact:displayName>
<ipxact:description>Use measured value (available in TRV_DELAY) + SSP_OFFSET.</ipxact:description>
<ipxact:displayName>SSP_SRC_MEAS_N_OFFSET</ipxact:displayName>
<ipxact:description>SSP position = TRV_DELAY (Measured Value) + SSP_OFFSET.</ipxact:description>
<ipxact:value>0</ipxact:value>
</ipxact:enumeratedValue>
<ipxact:enumeratedValue>
<ipxact:name>SSP_SRC_NO_SSP</ipxact:name>
<ipxact:displayName>SSP_SRC_NO_SSP</ipxact:displayName>
<ipxact:description>SSP is not used. Transmitter uses regular Sampling Point during Data Bit-Rate.</ipxact:description>
<ipxact:value>1</ipxact:value>
</ipxact:enumeratedValue>
</ipxact:enumeratedValues>
......
......@@ -144,7 +144,7 @@ entity bus_sampling is
can_tx :out std_logic;
------------------------------------------------------------------------
-- Memorz registers interface
-- Memory registers interface
------------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
......@@ -155,9 +155,12 @@ entity bus_sampling is
------------------------------------------------------------------------
-- Prescaler interface
------------------------------------------------------------------------
-- RX Trigger for Nominal Bit Time
-- RX Trigger
rx_trigger :in std_logic;
-- TX Trigger
tx_trigger :in std_logic;
-- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic;
......@@ -197,6 +200,8 @@ architecture rtl of bus_sampling is
(OTHERS => '0');
-- Saturation value of Secondary sampling point delay!
-- Saturate the value to one less than length of secondary sampling point
-- shift register to avoid overflow!
constant C_SSP_DELAY_SAT_VAL : natural := G_SSP_SHIFT_LENGTH - 1;
-----------------------------------------------------------------------------
......@@ -224,7 +229,6 @@ architecture rtl of bus_sampling is
-- Secondary sampling signal (sampling with transciever delay compensation)
signal sample_sec_i : std_logic;
signal sample_sec_comb : std_logic;
-- Delayed TX Data from TX Data shift register at position of secondary
-- sampling point.
......@@ -389,7 +393,7 @@ begin
clk => clk_sys, -- IN
res_n => shift_regs_res_q, -- IN
input => rx_trigger, -- IN
input => tx_trigger, -- IN
enable => ssp_sr_ce, -- IN
reg_stat => sample_sec_shift, -- OUT
......@@ -404,7 +408,7 @@ begin
-- Secondary sampling point address decoder. Secondary sampling point
-- is taken from SSP Shift register at position of transceiver delay.
----------------------------------------------------------------------------
sample_sec_comb <= sample_sec_shift(to_integer(unsigned(ssp_delay)));
sample_sec_i <= sample_sec_shift(to_integer(unsigned(ssp_delay)));
----------------------------------------------------------------------------
......@@ -430,24 +434,6 @@ begin
);
----------------------------------------------------------------------------
-- Registering secondary sampling point
----------------------------------------------------------------------------
ssp_gen_proc : process(res_n, clk_sys)
begin
if (res_n = G_RESET_POLARITY) then
sample_sec_i <= '0';
elsif rising_edge(clk_sys) then
if (ssp_reset = '1') then
sample_sec_i <= '0';
else
sample_sec_i <= sample_sec_comb;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Bit error detector
---------------------------------------------------------------------------
......
......@@ -77,25 +77,26 @@
-- | Flag | | |
-- +------+-------+ | |
-- | | |
-- | Measurement progress | |
-- | | |
-- +------v-------+ Transceiver XX | |
-- | Measurement progress | v
-- | | |----------| TRV
-- | ------------|------------------| Shadow | Delay
-- | | | | register |-------->
-- +------v-------+ Transceiver XX | |----------|
-- | Transceiver | Delay | X v |
-- | Delay +-------+-----> | X |
-- | Counter | | | X v
-- +--------------+ +--v--+ | X |------------| |----------| SSP
-- SSP offset | | | X | | | Shadow | Offset
-- -------------+-----> | + +--> | X+-| Saturation |->+ register |------->
-- | | | | X | | | |
-- | +-----+ | X |------------| |----------|
-- +----------------> | X v
-- | | X |----------| TRV
-- | XX | Shadow | Delay
-- |-------------------------------| register |------>
-- |----------|
-- -------------------> | + +--> | X+-| Saturation |->+ register |------->
-- | | | X | | | |
-- +-----+ | X |------------| |----------|
-- | X
-- | X
-- XX
--
--------------------------------------------------------------------------------
-- 02.01.2018 Created file
-- 02.01.2019 Created file
-- 28.05.2019 Modified to use only offset and offset + measured value!
--------------------------------------------------------------------------------
Library ieee;
......@@ -287,14 +288,12 @@ begin
----------------------------------------------------------------------------
-- Multiplexor for selected secondary sampling point delay. Selects:
-- 1. Measured trv_delay.
-- 2. Measured trv_delay + ssp_offset
-- 3. ssp_offset
-- 1. Measured trv_delay + ssp_offset
-- 2. ssp_offset only.
----------------------------------------------------------------------------
with ssp_delay_select select ssp_delay_nxt <=
'0' & trv_delay_ctr_reg when SSP_SRC_MEASURED ,
trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,
'0' & ssp_offset when SSP_SRC_OFFSET ,
'0' & ssp_offset when SSP_SRC_OFFSET,
(OTHERS => '0') when others;
----------------------------------------------------------------------------
......
......@@ -424,6 +424,9 @@ architecture rtl of protocol_control is
-- Bus off restart
signal drv_bus_off_reset : std_logic;
-- Secondary sampling point configuration
signal drv_ssp_delay_select : std_logic_vector(1 downto 0);
-----------------------------------------------------------------------------
-- Internal signals
......@@ -595,6 +598,8 @@ begin
drv_fd_type <= drv_bus(DRV_FD_TYPE_INDEX);
drv_int_loopback_ena <= drv_bus(DRV_INT_LOOBACK_ENA_INDEX);
drv_bus_off_reset <= drv_bus(DRV_ERR_CTR_CLR);
drv_ssp_delay_select <= drv_bus(DRV_SSP_DELAY_SELECT_HIGH downto
DRV_SSP_DELAY_SELECT_LOW);
---------------------------------------------------------------------------
-- TX Data word endian swapper
......@@ -638,6 +643,7 @@ begin
drv_retr_lim_ena => drv_retr_lim_ena, -- IN
drv_int_loopback_ena => drv_int_loopback_ena,-- IN
drv_can_fd_ena => drv_can_fd_ena, -- IN
drv_ssp_delay_select => drv_ssp_delay_select,-- IN
is_control => is_control, -- OUT
is_data => is_data, -- OUT
is_stuff_count => is_stuff_count, -- OUT
......
......@@ -120,6 +120,9 @@ entity protocol_control_fsm is
-- Reception of CAN FD Frames is enabled
drv_can_fd_ena :in std_logic;
-- Secondary sampling point delay select
drv_ssp_delay_select :in std_logic_vector(1 downto 0);
-- Control field is being transmitted
is_control :out std_logic;
......@@ -601,13 +604,15 @@ architecture rtl of protocol_control_fsm is
signal sp_control_switch_data : std_logic;
signal sp_control_switch_nominal : std_logic;
-- Secondary sampling point is used
signal switch_to_ssp : std_logic;
signal sp_control_ce : std_logic;
signal sp_control_d : std_logic_vector(1 downto 0);
signal sp_control_q : std_logic_vector(1 downto 0);
-- Secondary sampling point shift register reset
signal ssp_reset_d : std_logic;
signal ssp_reset_q : std_logic;
signal ssp_reset_i : std_logic;
-- Synchronisation control
signal sync_control_d : std_logic_vector(1 downto 0);
......@@ -1250,7 +1255,7 @@ begin
sp_control_switch_nominal <= '0';
-- Secondary sampling point measurement
ssp_reset_d <= '0';
ssp_reset_i <= '0';
trv_delay_calib <= '0';
-- Fault confinement
......@@ -1565,7 +1570,7 @@ begin
if (tran_frame_type = NORMAL_CAN) then
tx_dominant <= '1';
else
ssp_reset_d <= '1';
ssp_reset_i <= '1';
end if;
end if;
......@@ -1632,7 +1637,7 @@ begin
if (is_transmitter = '1' and tran_frame_type = NORMAL_CAN) then
tx_dominant <= '1';
else
ssp_reset_d <= '1';
ssp_reset_i <= '1';
end if;
if (drv_can_fd_ena = FDE_DISABLE and rx_data = RECESSIVE) then
......@@ -2401,12 +2406,19 @@ begin
-----------------------------------------------------------------------
-- Switching of Bit-rate
-----------------------------------------------------------------------
sp_control_d <= NOMINAL_SAMPLE when (sp_control_switch_nominal = '1') else
DATA_SAMPLE when (sp_control_switch_data = '1' and
is_receiver = '1')
else
SECONDARY_SAMPLE when (sp_control_switch_data = '1') else
sp_control_q;
switch_to_ssp <= '1' when (sp_control_switch_data = '1' and
is_transmitter = '1' and
drv_ssp_delay_select /= SSP_SRC_NO_SSP)
else
'0';
sp_control_d <= NOMINAL_SAMPLE when (sp_control_switch_nominal = '1')
else
SECONDARY_SAMPLE when (switch_to_ssp = '1')
else
DATA_SAMPLE when (sp_control_switch_data = '1')
else
sp_control_q;
sp_control_ce <= '1' when (sp_control_switch_nominal = '1') else
'1' when (sp_control_switch_data = '1') else
......@@ -2423,24 +2435,7 @@ begin
end if;
end process;
-----------------------------------------------------------------------
-- Secondary sampling point reset
-----------------------------------------------------------------------
dff_arst_ssp_reset_inst : dff_arst
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
clk => clk_sys,
input => ssp_reset_d,
ce => '1',
output => ssp_reset_q
);
---------------------------------------------------------------------------
-- Indicates that Error or Overload flag is being transmitted! Can't
-- be part of current state, since it must be valid also during
......@@ -2582,7 +2577,7 @@ begin
txtb_hw_cmd <= txtb_hw_cmd_q;
sp_control <= sp_control_q;
tran_valid <= txtb_hw_cmd_q.valid;
ssp_reset <= ssp_reset_q;
ssp_reset <= ssp_reset_i;
rx_clear <= rx_clear_q;
sync_control <= sync_control_q;
txtb_ptr <= txtb_ptr_q;
......
......@@ -823,7 +823,7 @@ begin
ssp_reset => ssp_reset, -- OUT
trv_delay_calib => trv_delay_calib, -- OUT
bit_error => bit_error, -- IN
sample_sec => sample_sec -- OUT
sample_sec => sample_sec -- IN
);
......@@ -891,6 +891,7 @@ begin
-- Prescaler interface
rx_trigger => rx_triggers(1), -- IN
tx_trigger => tx_trigger, -- IN
sync_edge => sync_edge, -- OUT
-- CAN Core Interface
......
This diff is collapsed.
......@@ -206,9 +206,12 @@ package can_components is
------------------------------------------------------------------------
-- Prescaler interface
------------------------------------------------------------------------
-- RX Trigger for Nominal Bit Time
-- RX Trigger
rx_trigger :in std_logic;
-- TX Trigger
tx_trigger :in std_logic;
-- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic;
......@@ -1404,6 +1407,9 @@ package can_components is
-- Reception of CAN FD Frames is enabled
drv_can_fd_ena :in std_logic;
-- Secondary sampling point delay select
drv_ssp_delay_select :in std_logic_vector(1 downto 0);
-- Arbitration field is being transmitted
is_arbitration :out std_logic;
......
......@@ -103,7 +103,7 @@ package can_config is
constant C_SJW_DBT_WIDTH : natural := 5;
-- Secondary sampling point Shift registers length
constant C_SSP_SHIFT_LENGTH : natural := 130;
constant C_SSP_SHIFT_LENGTH : natural := 128;
-- Depth of FIFO Cache for TX Data
constant C_TX_CACHE_DEPTH : natural := 8;
......
......@@ -304,7 +304,7 @@ package can_fd_register_map is
(address => SSP_CFG_ADR,
size => 16,
reg_type => reg_read_write,
reset_val => "00000000000000000000000000000000"),
reset_val => "00000000000001000000000000000000"),
(address => RX_COUNTER_ADR,
size => 32,
reg_type => reg_read_only,
......@@ -1257,8 +1257,8 @@ package can_fd_register_map is
------------------------------------------------------------------------------
-- SSP_CFG register
--
-- Configuration of Secondary sampling point which is used for Transmitter in
-- Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.
-- Configuration of Secondary Sampling Point which is used by Transmitter in D
-- ata Bit-Rate. This register should be modified only when SETTINGS[ENA]=0.
------------------------------------------------------------------------------
constant SSP_OFFSET_L : natural := 16;
constant SSP_OFFSET_H : natural := 22;
......@@ -1266,12 +1266,12 @@ package can_fd_register_map is
constant SSP_SRC_H : natural := 25;
-- "SSP_SRC" field enumerated values
constant SSP_SRC_MEASURED : std_logic_vector(1 downto 0) := "00";
constant SSP_SRC_MEAS_N_OFFSET : std_logic_vector(1 downto 0) := "01";
constant SSP_SRC_MEAS_N_OFFSET : std_logic_vector(1 downto 0) := "00";
constant SSP_SRC_NO_SSP : std_logic_vector(1 downto 0) := "01";
constant SSP_SRC_OFFSET : std_logic_vector(1 downto 0) := "10";
-- SSP_CFG register reset values
constant SSP_OFFSET_RSTVAL : std_logic_vector(6 downto 0) := "0000000";
constant SSP_OFFSET_RSTVAL : std_logic_vector(6 downto 0) := "0000100";
constant SSP_SRC_RSTVAL : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
......
......@@ -748,7 +748,7 @@ begin
data_width => 16 ,
data_mask => "0000001101111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
reset_value => "0000000000000100" ,
auto_clear => "0000000000000000"
)
port map(
......
......@@ -883,17 +883,17 @@ begin
)
port map(
-- Clocks and Asynchronous reset
clk_sys => clk_sys,
res_n => res_n,
clk_sys => clk_sys, -- IN
res_n => res_n, -- IN
-- Port A - Write (from CAN Core)
port_a_address => RAM_write_address,
port_a_data_in => memory_write_data,
port_a_write => RAM_write,
port_a_address => RAM_write_address, -- IN
port_a_data_in => memory_write_data, -- IN
port_a_write => RAM_write, -- IN
-- Port B - Read (from Memory registers)
port_b_address => RAM_read_address,
port_b_data_out => RAM_data_out
port_b_address => RAM_read_address, -- IN
port_b_data_out => RAM_data_out -- OUT
);
-- Memory written either on regular write or Extra timestamp write
......
......@@ -226,17 +226,17 @@ begin
)
port map(
-- Clock and Asynchronous reset
clk_sys => clk_sys,
res_n => res_n,
clk_sys => clk_sys, -- IN
res_n => res_n, -- IN
-- Port A - Write (from Memory registers)
port_a_address => txtb_port_a_address,
port_a_data_in => txtb_port_a_data,
port_a_write => RAM_write,
port_a_address => txtb_port_a_address, -- IN
port_a_data_in => txtb_port_a_data, -- IN
port_a_write => RAM_write, -- IN
-- Port B - Read (from CAN Core)
port_b_address => RAM_read_address,
port_b_data_out => txtb_port_b_data
port_b_address => RAM_read_address, -- IN
port_b_data_out => txtb_port_b_data -- OUT
);
......@@ -249,20 +249,20 @@ begin
G_ID => G_ID
)
port map(
clk_sys => clk_sys,
res_n => res_n,
clk_sys => clk_sys, -- IN
res_n => res_n, -- IN
txtb_sw_cmd => txtb_sw_cmd,
sw_cbs => sw_cbs,
txtb_sw_cmd => txtb_sw_cmd, -- IN
sw_cbs => sw_cbs, -- IN
txtb_hw_cmd => txtb_hw_cmd,
hw_cbs => hw_cbs,
is_bus_off => is_bus_off,
txtb_hw_cmd => txtb_hw_cmd, -- IN
hw_cbs => hw_cbs, -- IN
is_bus_off => is_bus_off, -- IN
txtb_user_accessible => txtb_user_accessible,
txtb_hw_cmd_int => txtb_hw_cmd_int,
txtb_state => txtb_state,
txtb_ready => txtb_ready
txtb_user_accessible => txtb_user_accessible, -- OUT
txtb_hw_cmd_int => txtb_hw_cmd_int, -- OUT
txtb_state => txtb_state, -- OUT
txtb_ready => txtb_ready -- OUT
);
......
......@@ -3,27 +3,12 @@ proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "logger_size" -parent ${Page_0}
ipgui::add_param $IPINST -name "rx_buffer_size" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_be" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_filtA" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_filtB" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_filtC" -parent ${Page_0}
ipgui::add_param $IPINST -name "sup_range" -parent ${Page_0}
ipgui::add_param $IPINST -name "tx_time_sup" -parent ${Page_0}
ipgui::add_param $IPINST -name "use_logger" -parent ${Page_0}
ipgui::add_param $IPINST -name "use_sync" -parent ${Page_0}
}
proc update_PARAM_VALUE.logger_size { PARAM_VALUE.logger_size } {
# Procedure called to update logger_size when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.logger_size { PARAM_VALUE.logger_size } {
# Procedure called to validate logger_size
return true
}
proc update_PARAM_VALUE.rx_buffer_size { PARAM_VALUE.rx_buffer_size } {
......@@ -35,15 +20,6 @@ proc validate_PARAM_VALUE.rx_buffer_size { PARAM_VALUE.rx_buffer_size } {
return true
}
proc update_PARAM_VALUE.sup_be { PARAM_VALUE.sup_be } {
# Procedure called to update sup_be when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.sup_be { PARAM_VALUE.sup_be } {
# Procedure called to validate sup_be
return true
}
proc update_PARAM_VALUE.sup_filtA { PARAM_VALUE.sup_filtA } {
# Procedure called to update sup_filtA when any of the dependent parameters in the arguments change
}
......@@ -80,49 +56,11 @@ proc validate_PARAM_VALUE.sup_range { PARAM_VALUE.sup_range } {
return true
}
proc update_PARAM_VALUE.tx_time_sup { PARAM_VALUE.tx_time_sup } {
# Procedure called to update tx_time_sup when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.tx_time_sup { PARAM_VALUE.tx_time_sup } {
# Procedure called to validate tx_time_sup
return true
}
proc update_PARAM_VALUE.use_logger { PARAM_VALUE.use_logger } {
# Procedure called to update use_logger when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.use_logger { PARAM_VALUE.use_logger } {
# Procedure called to validate use_logger
return true
}
proc update_PARAM_VALUE.use_sync { PARAM_VALUE.use_sync } {
# Procedure called to update use_sync when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.use_sync { PARAM_VALUE.use_sync } {
# Procedure called to validate use_sync
return true
}
proc update_MODELPARAM_VALUE.use_logger { MODELPARAM_VALUE.use_logger PARAM_VALUE.use_logger } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.use_logger}] ${MODELPARAM_VALUE.use_logger}
}
proc update_MODELPARAM_VALUE.rx_buffer_size { MODELPARAM_VALUE.rx_buffer_size PARAM_VALUE.rx_buffer_size } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.rx_buffer_size}] ${MODELPARAM_VALUE.rx_buffer_size}
}
proc update_MODELPARAM_VALUE.use_sync { MODELPARAM_VALUE.use_sync PARAM_VALUE.use_sync } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.use_sync}] ${MODELPARAM_VALUE.use_sync}
}
proc update_MODELPARAM_VALUE.sup_filtA { MODELPARAM_VALUE.sup_filtA PARAM_VALUE.sup_filtA } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.sup_filtA}] ${MODELPARAM_VALUE.sup_filtA}
......@@ -142,19 +80,3 @@ proc update_MODELPARAM_VALUE.sup_range { MODELPARAM_VALUE.sup_range PARAM_VALUE.
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.sup_range}] ${MODELPARAM_VALUE.sup_range}
}
proc update_MODELPARAM_VALUE.tx_time_sup { MODELPARAM_VALUE.tx_time_sup PARAM_VALUE.tx_time_sup } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.tx_time_sup}] ${MODELPARAM_VALUE.tx_time_sup}
}
proc update_MODELPARAM_VALUE.sup_be { MODELPARAM_VALUE.sup_be PARAM_VALUE.sup_be } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.sup_be}] ${MODELPARAM_VALUE.sup_be}
}
proc update_MODELPARAM_VALUE.logger_size { MODELPARAM_VALUE.logger_size PARAM_VALUE.logger_size } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.logger_size}] ${MODELPARAM_VALUE.logger_size}
}
......@@ -251,12 +251,12 @@ package CANtestLib is
-- SSP (Secondary Sampling Point) configuration options
type SSP_set_command_type is (
ssp_measured,
ssp_meas_n_offset,
ssp_no_ssp,
ssp_offset
);
-- Use only TRV_DELAY
-- Use TRV_DELAY + fixed offset given by user
-- Don't use SSP!
-- Use only offset given by user
-- Protocol control Debug values
......@@ -4481,12 +4481,12 @@ package body CANtestLib is
(OTHERS => '0');
begin
case ssp_source is
when ssp_measured =>
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_MEASURED; --"00";
when ssp_meas_n_offset =>
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_MEAS_N_OFFSET; --"01";
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_MEAS_N_OFFSET;
when ssp_no_ssp =>
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_NO_SSP;
when ssp_offset =>
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_OFFSET; --"10";
data(SSP_SRC_H downto SSP_SRC_L) := SSP_SRC_OFFSET;
when others =>
error("Unsupported SSP type.");
end case;
......