...
 
Commits (2)
......@@ -368,7 +368,7 @@ begin
clk => clk_sys, -- IN
input => shift_regs_res_d, -- IN
load => '1', -- IN
ce => '1', -- IN
output => shift_regs_res_q -- OUT
);
......
......@@ -222,7 +222,7 @@ begin
clk => clk_sys,
input => destuff_enable,
load => '1',
ce => '1',
output => enable_prev
);
......@@ -297,7 +297,7 @@ begin
clk => clk_sys,
input => fixed_prev_d,
load => destuff_enable,
ce => destuff_enable,
output => fixed_prev_q
);
......@@ -411,7 +411,7 @@ begin
clk => clk_sys,
input => destuffed_d,
load => '1',
ce => '1',
output => destuffed_q
);
......@@ -438,7 +438,7 @@ begin
clk => clk_sys,
input => error_reg_d,
load => '1',
ce => '1',
output => error_reg_q
);
......@@ -468,7 +468,7 @@ begin
clk => clk_sys,
input => prev_val_d,
load => '1',
ce => '1',
output => prev_val_q
);
......
......@@ -242,7 +242,7 @@ begin
clk => clk_sys,
input => stuff_enable,
load => '1',
ce => '1',
output => enable_prev
);
......@@ -278,7 +278,7 @@ begin
clk => clk_sys,
input => fixed_reg_nxt,
load => stuff_enable,
ce => stuff_enable,
output => fixed_reg
);
......@@ -435,7 +435,7 @@ begin
clk => clk_sys,
input => data_out_nxt,
load => data_out_load,
ce => data_out_load,
output => data_out_int
);
......@@ -467,7 +467,7 @@ begin
clk => clk_sys,
input => halt_reg_nxt,
load => '1',
ce => '1',
output => halt_reg
);
......
......@@ -108,46 +108,99 @@ end entity;
architecture rtl of bus_traffic_counters is
signal tx_ctr_int : std_logic_vector(31 downto 0);
signal rx_ctr_int : std_logic_vector(31 downto 0);
signal tx_ctr_i : std_logic_vector(31 downto 0);
signal rx_ctr_i : std_logic_vector(31 downto 0);
-- Input selector
signal sel : std_logic;
-- Selected value to increment
signal sel_value : std_logic_vector(31 downto 0);
signal sel_value : unsigned(31 downto 0);
-- Incremented value by 1
signal inc_value : std_logic_vector(31 downto 0);
signal inc_value : unsigned(31 downto 0);
-- Reset signals for counters (registered, to avoid glitches)
signal tx_ctr_rst_d : std_logic;
signal tx_ctr_rst_q : std_logic;
signal rx_ctr_rst_d : std_logic;
signal rx_ctr_rst_q : std_logic;
begin
tx_ctr <= tx_ctr_int;
rx_ctr <= rx_ctr_int;
tx_ctr <= tx_ctr_i;
rx_ctr <= rx_ctr_i;
-- Input selector
sel <= '1' when (inc_tx_ctr = '1') else
'0';
-- Multiplexor between TX and RX value to increment
sel_value <= tx_ctr_int when (sel = '1') else
rx_ctr_int;
sel_value <= unsigned(tx_ctr_i) when (sel = '1') else
unsigned(rx_ctr_i);
-- Incremented value of either TX or RX counter
inc_value <= std_logic_vector(to_unsigned(
to_integer(unsigned(sel_value)) + 1, sel_value'length));
inc_value <= sel_value + 1;
----------------------------------------------------------------------------
-- Reset registers
----------------------------------------------------------------------------
tx_ctr_rst_d <= G_RESET_POLARITY when (res_n = G_RESET_POLARITY) else
G_RESET_POLARITY when (clear_tx_ctr = '1') else
(not G_RESET_POLARITY);
rx_ctr_rst_d <= G_RESET_POLARITY when (res_n = G_RESET_POLARITY) else
G_RESET_POLARITY when (clear_rx_ctr = '1') else
(not G_RESET_POLARITY);
tx_ctr_res_inst : dff_arst
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '1'
)
port map(
-- Keep without reset! We can't use res_n to avoid reset recovery!
-- This does not mind, since stable value will be here one clock cycle
-- after reset by res_n.
arst => '1', -- IN
clk => clk_sys, -- IN
input => tx_ctr_rst_d, -- IN
ce => '1', -- IN
output => tx_ctr_rst_q -- OUT
);
rx_ctr_res_inst : dff_arst
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '1'
)
port map(
-- Keep without reset! We can't use res_n to avoid reset recovery!
-- This does not mind, since stable value will be here one clock cycle
-- after reset by res_n.
arst => '1', -- IN
clk => clk_sys, -- IN
input => rx_ctr_rst_d, -- IN
ce => '1', -- IN
output => rx_ctr_rst_q -- OUT
);
----------------------------------------------------------------------------
-- TX Counter register
----------------------------------------------------------------------------
tx_ctr_proc : process(clk_sys, res_n, clear_tx_ctr)
tx_ctr_proc : process(clk_sys, tx_ctr_rst_q)
begin
if (res_n = G_RESET_POLARITY or clear_tx_ctr = '1') then
tx_ctr_int <= (OTHERS => '0');
if (tx_ctr_rst_q = G_RESET_POLARITY) then
tx_ctr_i <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (inc_tx_ctr = '1') then
tx_ctr_int <= inc_value;
tx_ctr_i <= std_logic_vector(inc_value);
end if;
end if;
end process;
......@@ -156,14 +209,14 @@ begin
----------------------------------------------------------------------------
-- RX Counter register
----------------------------------------------------------------------------
rx_ctr_proc : process(clk_sys, res_n, clear_rx_ctr)
rx_ctr_proc : process(clk_sys, rx_ctr_rst_q)
begin
if (res_n = G_RESET_POLARITY or clear_rx_ctr = '1') then
rx_ctr_int <= (OTHERS => '0');
if (rx_ctr_rst_q = G_RESET_POLARITY) then
rx_ctr_i <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (inc_rx_ctr = '1') then
rx_ctr_int <= inc_value;
rx_ctr_i <= std_logic_vector(inc_value);
end if;
end if;
end process;
......
......@@ -811,7 +811,7 @@ begin
clk => clk_sys,
input => tx_trigger,
load => '1',
ce => '1',
output => tx_trigger_q
);
......@@ -837,7 +837,7 @@ begin
clk => clk_sys,
input => bds_data_in,
load => rx_triggers(1),
ce => rx_triggers(1),
output => crc_data_rx_wbs
);
......
......@@ -223,8 +223,9 @@ begin
port map(
arst => res_n, -- IN
clk => clk_sys, -- IN
input => set_err_active, -- IN
load => '1', -- IN
ce => '1', -- IN
output => set_err_active_q -- OUT
);
......
......@@ -2352,8 +2352,10 @@ begin
port map(
arst => res_n,
clk => clk_sys,
input => rx_clear_d,
load => '1',
ce => '1',
output => rx_clear_q
);
......@@ -2421,8 +2423,10 @@ begin
port map(
arst => res_n,
clk => clk_sys,
input => ssp_reset_d,
load => '1',
ce => '1',
output => ssp_reset_q
);
......
......@@ -69,7 +69,7 @@ entity dff_arst is
input : in std_logic;
-- Clock enable (CE)
load : in std_logic;
ce : in std_logic;
-- Data output (Q)
output : out std_logic
......@@ -86,7 +86,7 @@ begin
output <= G_RST_VAL;
elsif (rising_edge(clk)) then
if (load = '1') then
if (ce = '1') then
output <= input;
end if;
end if;
......
......@@ -72,7 +72,7 @@ package cmn_lib is
input : in std_logic;
-- Clock enable (CE)
load : in std_logic;
ce : in std_logic;
-- Data output (Q)
output : out std_logic
......
......@@ -525,7 +525,7 @@ begin
clk => clk_sys, -- IN
input => rx_buf_res_d, -- IN
load => '1', -- IN
ce => '1', -- IN
output => rx_buf_res_q -- OUT
);
......@@ -836,7 +836,7 @@ begin
-- memory, and there is not enough free space, data overrun flag will be
-- set, and no further writes will be executed.
----------------------------------------------------------------------------
dor_proc : process(res_n, clk_sys, drv_erase_rx)
dor_proc : process(res_n, rx_buf_res_q)
begin
if (rx_buf_res_q = G_RESET_POLARITY) then
data_overrun_r <= '0';
......