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Commits (4)
This diff is collapsed.
......@@ -643,6 +643,9 @@ architecture rtl of protocol_control_fsm is
-- places than enabled!
signal bit_err_disable : std_logic;
-- Bit Error is disabled for receiver in most of the frame!
signal bit_err_disable_receiver : std_logic;
-- TXT Buffer pointer
signal txtb_ptr_d : natural range 0 to 19;
signal txtb_ptr_q : natural range 0 to 19;
......@@ -700,7 +703,8 @@ begin
arbitration_lost_condition <= '1' when (is_transmitter = '1' and
tx_data_wbs = RECESSIVE and
rx_data = DOMINANT)
rx_data = DOMINANT and
rx_trigger = '1')
else
'0';
......@@ -1243,6 +1247,7 @@ begin
crc_error_i <= '0';
bit_error_arb_i <= '0';
bit_err_disable <= '0';
bit_err_disable_receiver <= '0';
crc_clear_match_flag <= '0';
err_pos <= ERC_POS_OTHER;
......@@ -1446,6 +1451,7 @@ begin
-------------------------------------------------------------------
when s_pc_ide =>
rx_store_ide_i <= '1';
bit_err_disable <= '1';
crc_enable <= '1';
txtb_ptr_d <= 1;
alc_id_field <= ALC_IDE;
......@@ -1565,6 +1571,7 @@ begin
err_pos <= ERC_POS_CTRL;
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
if (is_transmitter = '1') then
if (tran_frame_type = NORMAL_CAN) then
......@@ -1585,6 +1592,7 @@ begin
trv_delay_calib <= '1';
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
if (is_transmitter = '1') then
tx_dominant <= '1';
......@@ -1606,6 +1614,7 @@ begin
perform_hsync <= '1';
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
if (is_transmitter = '1') then
tx_dominant <= '1';
......@@ -1627,6 +1636,7 @@ begin
err_pos <= ERC_POS_CTRL;
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
if (rx_data = DOMINANT) then
ctrl_ctr_pload_i <= '1';
......@@ -1652,6 +1662,7 @@ begin
err_pos <= ERC_POS_CTRL;
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
if (is_transmitter = '1' and tran_brs = BR_NO_SHIFT) then
tx_dominant <= '1';
......@@ -1673,6 +1684,7 @@ begin
err_pos <= ERC_POS_CTRL;
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
if (is_transmitter = '1' and is_err_active = '1') then
tx_dominant <= '1';
......@@ -1688,6 +1700,7 @@ begin
err_pos <= ERC_POS_CTRL;
crc_enable <= '1';
is_control <= '1';
bit_err_disable_receiver <= '1';
-- Address first Data Word in TXT Buffer RAM in advance to
-- account for DFF delay and RAM delay! Do it only when tran-
......@@ -1728,6 +1741,7 @@ begin
crc_enable <= '1';
is_data <= '1';
compl_ctr_ena_i <= '1';
bit_err_disable_receiver <= '1';
-- Address next word (the one after actually transmitted one),
-- so that when current word ends, TXT Buffer RAM already
......@@ -1772,6 +1786,7 @@ begin
err_pos <= ERC_POS_CRC;
crc_enable <= '1';
is_stuff_count <= '1';
bit_err_disable_receiver <= '1';
if (ctrl_ctr_zero = '1') then
ctrl_ctr_pload_val <= crc_length_i;
......@@ -1794,6 +1809,7 @@ begin
tx_shift_ena_i <= '1';
err_pos <= ERC_POS_CRC;
is_crc <= '1';
bit_err_disable_receiver <= '1';
if (is_fd_frame = '1') then
stuff_length <= std_logic_vector(to_unsigned(4, 3));
......@@ -2000,6 +2016,12 @@ begin
if (tx_frame_ready = '1' and go_to_suspend = '0') then
stuff_enable_set <= '1';
end if;
-- If we dont sample dominant, nor we have sth ready for
-- transmission, we go to Idle!
if (rx_data = RECESSIVE and tx_frame_ready = '0') then
set_idle <= '1';
end if;
-- First or second bit of intermission!
elsif (rx_data = DOMINANT) then
......@@ -2054,6 +2076,7 @@ begin
when s_pc_idle =>
perform_hsync <= '1';
crc_spec_enable <= '1';
bit_err_disable <= '1';
-- Address Identifier Word in TXT Buffer RAM in advance to
-- account for DFF delay and RAM delay!
......@@ -2339,7 +2362,11 @@ begin
txtb_hw_cmd_q.arbl <= '0';
txtb_hw_cmd_q.failed <= '0';
elsif (rising_edge(clk_sys)) then
txtb_hw_cmd_q <= txtb_hw_cmd_d;
if (rx_trigger = '1') then
txtb_hw_cmd_q <= txtb_hw_cmd_d;
else
txtb_hw_cmd_q <= ('0', '0', '0', '0', '0', '0');
end if;
end if;
end process;
......@@ -2477,6 +2504,18 @@ begin
no_pos_resync <= '1' when (is_transmitter = '1' and tx_data_wbs = DOMINANT)
else
'0';
---------------------------------------------------------------------------
-- Bit error is disabled:
-- 1. In arbitration field, there it is detected extra since only
-- transmitting dominant and receiving recessive is trated as bit error.
-- 2. For receiver during control, data, CRC fields!
---------------------------------------------------------------------------
bit_error_enable <= '0' when (bit_err_disable = '1') else
'0' when (bit_err_disable_receiver = '1' and
is_receiver = '1')
else
'1';
---------------------------------------------------------------------------
-- Retransmitt counter is manipulated only for one clock cycle
......@@ -2583,6 +2622,4 @@ begin
txtb_ptr <= txtb_ptr_q;
pc_state <= curr_state;
bit_error_enable <= not bit_err_disable;
end architecture;
\ No newline at end of file
......@@ -371,8 +371,8 @@ begin
-- severity error;
-- psl rx_buf_cmds_one_hot_asrt : assert always
-- (cmd_join = "0000" or cmd_join = "0001" or cmd_join = "0010"
-- or cmd_join = "0100" or cmd_join = "1000")
-- (now > 0 ps) -> (cmd_join = "0000" or cmd_join = "0001" or
-- cmd_join = "0010" or cmd_join = "0100" or cmd_join = "1000")
-- report "RX Buffer: RX Buffer commands should be one-hot encoded!"
-- severity error;
......
......@@ -137,8 +137,6 @@ package body message_filter_feature is
o.outcome := true;
CAN_generate_frame(rand_ctr, CAN_frame);
CAN_frame.brs := '0';
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 1600, 1601);
------------------------------------------------------------------------
-- Part 1 (Message filters disabled)
......
......@@ -92,14 +92,6 @@ package body overload_feature is
begin
o.outcome := true;
------------------------------------------------------------------------
-- Wait until unit comes out of integration. This is to make sure
-- that first frame will be transmitted and not that transition to
-- "interframe" will be from "off", directly after integration! This
-- transition goes directly to "interm_idle" and bit is correctly
-- interpreted as SOF and not Overload flag!
------------------------------------------------------------------------
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 2500, 3000);
------------------------------------------------------------------------
-- Generate CAN Frame and start transmission
......
......@@ -431,6 +431,10 @@ begin
CAN_enable_retr_limit(true, 0, ID_1, mem_bus(1));
CAN_enable_retr_limit(true, 0, ID_2, mem_bus(2));
-- Wait till integration is over!
CAN_wait_bus_on(ID_1, mem_bus(1));
CAN_wait_bus_on(ID_2, mem_bus(2));
info("RETR limit set");
-------------------------------------------------
-- Main test loop
......
......@@ -88,14 +88,6 @@ package body timestamp_options_feature is
begin
o.outcome := true;
------------------------------------------------------------------------
-- If this is the only test, wait until controller will come out
-- of integration phase!
------------------------------------------------------------------------
for i in 0 to 1700 loop
wait until rising_edge(mem_bus(1).clk_sys);
end loop;
------------------------------------------------------------------------
-- Configure timestamp options to the begining of CAN Frame.
------------------------------------------------------------------------
......
......@@ -108,10 +108,6 @@ package body tx_arb_time_tran_feature is
o.outcome := true;
------------------------------------------------------------------------
-- Wait until unit for sure comes out of integration.
------------------------------------------------------------------------
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 1600, 1601);
------------------------------------------------------------------------
-- Part 1
......
......@@ -107,10 +107,6 @@ package body txt_buffer_hazard_feature is
begin
o.outcome := true;
-- Wait till Integration phase is over
for i in 0 to 3000 loop
wait until rising_edge(mem_bus(1).clk_sys);
end loop;
-- Generate CAN frame
CAN_generate_frame(rand_ctr, CAN_frame);
......
......@@ -137,7 +137,6 @@ package body txtb_state_feature is
CAN_generate_frame(rand_ctr, CAN_frame);
CAN_frame.rtr := RTR_FRAME;
CAN_frame.frame_format := NORMAL_CAN;
wait_rand_cycles(rand_ctr, mem_bus(1).clk_sys, 1600, 1601);
CAN_enable_retr_limit(false, 0, ID_1, mem_bus(1));
for i in 1 to C_TXT_BUFFER_COUNT loop
......
......@@ -1395,6 +1395,21 @@ package CANtestLib is
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
-- Wait until a Node is in Error Active state! Actively polls on Fault state
-- register. Can be used after enabling CAN node to wait till integration
-- field is over!
--
-- Arguments:
-- ID Index of CTU CAN FD Core instance
-- mem_bus Avalon memory bus to execute the access on.
----------------------------------------------------------------------------
procedure CAN_wait_bus_on(
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
-- Calculate length of CAN Frame in bits (stuff bits not included).
......@@ -3642,6 +3657,19 @@ package body CANtestLib is
end loop;
end procedure;
procedure CAN_wait_bus_on(
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
)is
variable fault_state : SW_fault_state;
begin
get_fault_state(fault_state, ID, mem_bus);
while (fault_state /= fc_error_active) loop
get_fault_state(fault_state, ID, mem_bus);
end loop;
end procedure;
procedure CAN_calc_frame_length(
......