1. 03 Aug, 2019 2 commits
  2. 23 Jul, 2019 6 commits
  3. 12 Jul, 2019 5 commits
  4. 07 Jul, 2019 4 commits
  5. 02 Jul, 2019 1 commit
  6. 01 Jul, 2019 6 commits
  7. 22 Jun, 2019 3 commits
  8. 21 Jun, 2019 2 commits
    • Ille, Ondrej, Ing.'s avatar
      src: Use CRC init vector loading controlled by Protocol control FSM. · 0f1153da
      Ille, Ondrej, Ing. authored
      Init vector is not loaded on by edge on enable but by PC FSM. This
      allows removing special mux on datapath in Bit-destuffing. Thanks
      to this, when H-sync edge occurs in Idle right in Process pipeline
      stage, unit properly samples recessive and not dominant and measures
      length of arbitration field properly.
      
      CRC Init vector is always loaded in situations:
      1. In Intermission (first or second bit), does not mind being loaded
         twice. Can't be loaded in third one since this can already be SOF
         and first bit of calculation might be executed.
      2. Transfer to Idle after integration or reintegration.
      
      Note that there is always intermission after every frame so we are
      sure that init vector will get loaded! Loading post re-integration
      and integration is done just to be sure it is loaded after unit
      just joins the bus.
      0f1153da
    • Ille, Ondrej, Ing.'s avatar
      0adc59be
  9. 16 Jun, 2019 2 commits
  10. 14 Jun, 2019 4 commits
  11. 13 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Remove second bit time counters. · e27ab4b2
      Ille, Ondrej, Ing. authored
      Implemented sample control bypassing scheme which allows
      updating sample control right in first cycle after bit
      rate shift. Added extra load of expected segment length
      register in BRS.
      e27ab4b2
  12. 10 Jun, 2019 1 commit
  13. 09 Jun, 2019 1 commit
  14. 07 Jun, 2019 2 commits