Commit fff5ef11 authored by Martin Jeřábek's avatar Martin Jeřábek

update gitignore, remove backup files

parent c1e500cd
Pipeline #1322 passed with stages
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/modelsim_project/work
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\begin_body
\begin_layout Title
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CAN FLEXIBLE DATA-RATE
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IP CORE
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PRODUCT BRIEF
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filename E:/Skola/CVUT-FEL/LEV.bmp
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Czech Technical University in Prague
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Faculty of electrical engineering
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Department of measurement
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Ondrej Ille
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August 2016
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Overview
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CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
1.0 and ISO CAN FD specification in single light-weight IP Core.
It is soft-core IP Core written in VHDL with only standard IEEE libraries
needed.
The main target of usage are FPGA applications and the core is available
as RTL.
It is optimized for inference of native hardware blocks such as SRAM memories
and multipliers in DSP blocks.
Generic settings achieve a high level of flexibility before synthesis.
It is posible to balance the core between high amount of features and small
size.
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The IP Core is accessed as memory mapped peripheria via Avalon bus.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO like RX buffer is available and two TX buffers are available.
Timestamps can be captured for various events on the CAN bus.
Additionally transmission of CAN frames can be triggered by external timestamp.
Asynchronous access is supported via rich interrupt settings.
Three Bit filters and one Range filter is available on received frames.
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The design is fully tested at RTL level as well as in real hardware with
Altera Cyclone IV FPGA series.
The automated test-framework in TCL is available within the core and it
provides an easy way of reproducing unit test, feature covering tests and
real bus simulation.
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Features
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CAN 2.0, CAN FD 1.0 and ISO CAN FD
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RTL VHDL (synthesis), TCL (testing)
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Pre-synthesis configurable features
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Avalon memory bus
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Timestamping and transmission at given time
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Optional event and error logging
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Fault confinement state manipulation
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Transceiver delay measurement
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Size 6 000 - 11 000 LUTs
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2 000 - 12 000 SRAM memory bits
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Synchronization output with time quantum
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Variety of interrupt sources
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Filtering of received frame
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Listen-only mode, Self-test mode,
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Acknowledge forbidden mode
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Up to 14 Mbit in
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Data
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bit-rate
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(with 100 Mhz Core clock)
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Driver in C available
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