Commit fdc2f2a6 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added Benchmark Project in Quartus and TCL script

implementation for benchmarking the resource usage
in Cyclone V with 7 different core configurations.
Added first benchmark result. The benchmarks are taken
post fitting.
parent c31d0c64
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
##
## Project advisor: Jiri Novak <jnovak@fel.cvut.cz>
## Department of Measurement (http://meas.fel.cvut.cz/)
## Faculty of Electrical Engineering (http://www.fel.cvut.cz)
## Czech Technical University (http://www.cvut.cz/)
##
## Permission is hereby granted, free of charge, to any person obtaining a copy
## of this VHDL component and associated documentation files (the "Component"),
## to deal in the Component without restriction, including without limitation
## the rights to use, copy, modify, merge, publish, distribute, sublicense,
## and/or sell copies of the Component, and to permit persons to whom the
## Component is furnished to do so, subject to the following conditions:
##
## The above copyright notice and this permission notice shall be included in
## all copies or substantial portions of the Component.
##
## THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
## AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
## FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
## IN THE COMPONENT.
##
## The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
## Anybody who wants to implement this IP core on silicon has to obtain a CAN
## protocol license from Bosch.
##
################################################################################
################################################################################
## Description:
## Quartus TCL script for automation of core resource requirements.
## Execute the script in Quartus project: Benchmark_project located
## in synthesis/Quartus.
################################################################################
load_package flow
load_package report
set CONFIG_COUNT 7
set i 1
set results [list]
## Name of CAN_top_level entity parameters
set PARAM_NAMES [ list "dummy" \
"use_logger" \
"rx_buffer_size" \
"use_FD_size" \
"use_sync" \
"ID" \
"sup_filtA" \
"sup_filtB" \
"sup_filtC" \
"sup_range" \
"tx_time_sup" \
"logger_size"
]
## List of synthesis configurations
set CFG_LIST [ list [ list "Minimal configuration" \
false 16 false true 1 false\
false false false false 8
] \
[ list "Minimal FD configuration" \
false 32 true true 1 false\
false false false false 8
] \
[ list "Small FD configuration" \
false 32 true true 1 true\
false false false true 8
] \
[ list "Medium FD configuration" \
false 32 true true 1 true\
false false true true 8
] \
[ list "Full FD configuration" \
false 32 true true 1 true\
true true true true 8
] \
[ list "Full FD configuration + Small logger" \
true 32 true true 1 true\
true true true true 8
] \
[ list "Full FD configuration + Big logger" \
true 32 true true 1 true\
true true true true 64
]
]
foreach config $CFG_LIST {
set act_cfg [lindex $config 0]
puts "Configuration name: ${act_cfg}"
# Set configuration to top level entity and compile
foreach par_name $PARAM_NAMES par_val $config {
set_parameter -entity "CAN_Wrapper" -name $par_name $par_val
}
execute_flow -compile
# Load report and get the results
load_report
set aluts [get_fitter_resource_usage -alut -used]
set aregs [get_fitter_resource_usage -reg -used]
set alms [get_fitter_resource_usage -alm -used]
set mbits [get_fitter_resource_usage -mem_bit -used]
lappend results [list $act_cfg [list "LUTs" $aluts] \
[list "REGs" $aregs] \
[list "ALMs" $alms] \
[list "Mbits" $mbits]
]
unload_report
}
puts " "
puts "CAN FD Benchmark results:"
foreach cfg_res $results {
puts $cfg_res
}
# Working with Altera Quartus II (Q2) and do proper versioning is not that easy
# but if you follow some rules it can be accomplished. :)
# This file should be placed into the main directory where the .qpf file is
# found. Generally Q2 throws all entities and so on in the main directory, but
# you can place all stuff also in separate folders. This approach is followed
# here. So when you create a new design create one or more folders where your
# entities will be located and put a .gitignore in there that overrides the
# ignores of this file, e.g. one single rule stating "!*" which allows now all
# type of files. When you add a MegaFunction or another entity to your design,
# simply add it to one of your private folders and Q2 will be happy and manage
# everything quite good. When you want to do versioning of your generated
# SOF/POF files, you can do this by redirecting the generated output to an own
# folder. To do this go to:
# "Assignments"
# -> "Settings
# -> "Compilation Process Settings"
# -> "Save project output files in specified directory"
# Now you can either place a .gitignore in the directory and allow the following
# list of types:
# !*.sof
# !*.pof
# or you create an own submodule in the folder to keep binary files out of your
# design.
# ignore Quartus II generated files
*sopc_*
*.jdi
*.ptf.*
*.sof
*.pof
*.qws
*.smsg
*_inst.vhd
*_generation_script*
*.done
*.txt
*.qarlog
*.rpt
*.summary
*.qws
*.cmp
*.eqn
*.html
*.jpg
*.bak
*.qar
*.sopc_builder
*example*
*~
*.sdc
*.tcl
*.pin
*.mif
*.hex
# ignore Quartus II generated folders
db/
incremental_db/
simulation/
timing/
testbench/
*_sim/
\ No newline at end of file
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 17:41:32 December 19, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "17:41:32 December 19, 2017"
# Revisions
PROJECT_REVISION = "Benchmark_project"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 17:41:32 December 19, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Benchmark_project_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEFA9F27C8
set_global_assignment -name TOP_LEVEL_ENTITY CAN_Wrapper
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:41:32 DECEMBER 19, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\registers_memory_interface"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\interrupts"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\event_logger"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\deprecated"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\can_core"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\bus_timing_synchronisation"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src\\buffers_message_handling"
set_global_assignment -name SEARCH_PATH "e:\\skola\\cvut-fel\\can_fd_ip_core\\src"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE CAN_Wrapper.vhd
set_global_assignment -name VHDL_FILE ../../src/rst_sync.vhd
set_global_assignment -name VHDL_FILE ../../src/Registers_Memory_Interface/canfd_registers.vhd
set_global_assignment -name VHDL_FILE ../../src/Interrupts/intManager.vhd
set_global_assignment -name VHDL_FILE ../../src/Event_Logger/logger.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/tranBuffer.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/protocolControl.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/operationControl.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/faultConf.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/CRC.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/core_top.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/bitStuffing_v2.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_Core/bitDeStuffing.vhd
set_global_assignment -name VHDL_FILE ../../src/Bus_Timing_Synchronisation/prescaler_v3.vhd
set_global_assignment -name VHDL_FILE ../../src/Bus_Timing_Synchronisation/busSync.vhd
set_global_assignment -name VHDL_FILE ../../src/Bus_Timing_Synchronisation/brs_comp.vhd
set_global_assignment -name VHDL_FILE ../../src/Buffers_Message_Handling/txtBuffer.vhd
set_global_assignment -name VHDL_FILE ../../src/Buffers_Message_Handling/txArbitrator.vhd
set_global_assignment -name VHDL_FILE ../../src/Buffers_Message_Handling/rxBuffer.vhd
set_global_assignment -name VHDL_FILE ../../src/Buffers_Message_Handling/messageFilter.vhd
set_global_assignment -name VHDL_FILE ../../src/ID_transfer.vhd
set_global_assignment -name VHDL_FILE ../../src/CANconstants.vhd
set_global_assignment -name VHDL_FILE ../../src/CANcomponents.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_top_level.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name TCL_SCRIPT_FILE ../../scripts/resource_benchmark.tcl
set_parameter -name cfg_indesdfdsfx 1
set_parameter -name cfg_index 1
set_parameter -name dummy "Minimal FD configuration"
set_parameter -name use_logger false
set_parameter -name rx_buffer_size 32
set_parameter -name use_FD_size true
set_parameter -name use_sync true
set_parameter -name ID 1
set_parameter -name sup_filtA false
set_parameter -name sup_filtB false
set_parameter -name sup_filtC false
set_parameter -name sup_range false
set_parameter -name tx_time_sup false
set_parameter -name logger_size 8
set_parameter -name dummy "Full FD configuration + Big logger"
set_parameter -name use_logger true
set_parameter -name rx_buffer_size 32
set_parameter -name use_FD_size true
set_parameter -name use_sync true
set_parameter -name ID 1
set_parameter -name sup_filtA true
set_parameter -name sup_filtB true
set_parameter -name sup_filtC true
set_parameter -name sup_range true
set_parameter -name tx_time_sup true
set_parameter -name logger_size 64
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
-- Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisor: Jiri Novak <jnovak@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Wrapper for testing the synthesis size with different options
--------------------------------------------------------------------------------
-- Revision History:
-- 19.12.2017 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
use work.CANcomponents.ALL;
entity CAN_Wrapper is
generic (
constant use_logger : boolean := false;
constant rx_buffer_size : natural := 32;
constant useFDSize : boolean := true;
constant use_sync : boolean:= true;
constant ID : natural:= 1;
constant sup_filtA : boolean:= true;
constant sup_filtB : boolean:= true;
constant sup_filtC : boolean:= true;
constant sup_range : boolean:= true;
constant tx_time_sup : boolean:= true;
constant logger_size : natural:= 8
);
port (
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal scs : in std_logic; --Chip select
signal srd : in std_logic; --Serial read
signal swr : in std_logic; --Serial write
signal int : out std_logic;
signal CAN_tx : out std_logic;
signal CAN_rx : in std_logic;
signal time_quanta_clk : out std_logic;
signal timestamp : in std_logic_vector(63 downto 0)
);
end entity CAN_Wrapper;
architecture rtl of CAN_Wrapper is
-- --Minimal configuration
-- (
-- use_logger => false,
-- rx_buffer_size => 16,
-- useFDSize => false,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => false,
-- sup_filtB => false,
-- sup_filtC => false,
-- sup_range => false,
-- tx_time_sup => false,
-- logger_size => 8
-- ),
--
-- --Minimal FD configuration
-- (
-- use_logger => false,
-- rx_buffer_size => 32,
-- useFDSize => true,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => false,
-- sup_filtB => false,
-- sup_filtC => false,
-- sup_range => false,
-- tx_time_sup => false,
-- logger_size => 8
-- ),
--
-- --Small FD configuration
-- (
-- use_logger => false,
-- rx_buffer_size => 32,
-- useFDSize => true,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => true,
-- sup_filtB => false,
-- sup_filtC => false,
-- sup_range => false,
-- tx_time_sup => true,
-- logger_size => 8
-- ),
--
-- --Medium FD configuration
-- (
-- use_logger => false,
-- rx_buffer_size => 64,
-- useFDSize => true,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => true,
-- sup_filtB => false,
-- sup_filtC => false,
-- sup_range => true,
-- tx_time_sup => true,
-- logger_size => 8
-- ),
--
-- --Full FD configuration
-- (
-- use_logger => false,
-- rx_buffer_size => 128,
-- useFDSize => true,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => true,
-- sup_filtB => true,
-- sup_filtC => true,
-- sup_range => true,
-- tx_time_sup => true,
-- logger_size => 8
-- ),
--
-- --Full FD configuration + Small Logger
-- (
-- use_logger => true,
-- rx_buffer_size => 128,
-- useFDSize => true,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => true,
-- sup_filtB => true,
-- sup_filtC => true,
-- sup_range => true,
-- tx_time_sup => true,
-- logger_size => 8
-- ),
--
-- --Full FD configuration + Big Logger
-- (
-- use_logger => true,
-- rx_buffer_size => 128,
-- useFDSize => true,
-- use_sync => true,
-- ID => 1,
-- sup_filtA => true,
-- sup_filtB => true,
-- sup_filtC => true,
-- sup_range => true,
-- tx_time_sup => true,
-- logger_size => 64
-- )
-- );
begin
CAN_comp:CAN_top_level
generic map(
use_logger => use_logger,
rx_buffer_size => rx_buffer_size,
useFDSize => useFDSize,
use_sync => use_sync,
ID => ID,
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
sup_filtC => sup_filtC,
sup_range => sup_range,
tx_time_sup => tx_time_sup,
logger_size => logger_size
)
port map(
clk_sys => clk_sys,
res_n => res_n,
data_in => data_in,
data_out => data_out,
adress => adress,
scs => scs,
srd => srd,
swr => swr,
int => int,
CAN_tx => CAN_tx,
CAN_rx => CAN_rx,
time_quanta_clk => time_quanta_clk,
timestamp => timestamp
);
end architecture;
Info: Using NativeLink to launch synthesis Tool
Synthesis tool <None> is not supported by NativeLink
Error: NativeLink flow failed to complete synthesis
================The following information is provided to Debug NativeLink Script=================
Nativelink TCL script failed with errorCode: POSIX ENOENT {no such file or directory}
Nativelink TCL script failed with errorInfo: couldn't open "C:/intelFPGA_lite/16.1/quartus/bin64/tclIndex": no such file or directory
while executing
"open [file join $dir tclIndex]"
PATH Environment Variable is set to : c:\intelfpga_lite\16.1\quartus\bin64\;c:\intelfpga_lite\16.1\quartus\bin64\;C:\altera\91sp2\quartus;C:\oraclexe\app\oracle\product\11.2.0\server\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\CollabNet;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2014a\runtime\win64;C:\Program Files\MATLAB\R2014a\bin;C:\Program Files (x86)\RemObjects Software\Elements\bin;C:\intelFPGA_lite\16.1\quartus\bin;C:\Program Files (x86)\OpenSSH\bin;C:\Program Files (x86)\SuperSequencer\prog106x;"C:\Program Files (x86)\Graphviz2.16\Bin";C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files (x86)\PuTTY\;C:\Program Files (x86)\Skype\Phone\;C:\Program Files\MiKTeX 2.9\miktex\bin\x64\;C:\Program Files (x86)\LyX 2.2\Perl\bin;C:\Cadence\SPB_16.6\openaccess\bin\win32\opt;C:\Cadence\SPB_16.6\tools\capture;C:\Cadence\SPB_16.6\tools\pspice;C:\Cadence\SPB_16.6\tools\specctra\bin;C:\Cadence\SPB_16.6\tools\fet\bin;C:\Cadence\SPB_16.6\tools\libutil\bin;C:\Cadence\SPB_16.6\tools\bin;C:\Cadence\SPB_16.6\tools\pcb\bin;C:\altera\91sp2\modelsim_ase\win32aloem
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