Commit e9635c0a authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Remove IPT checker. Not needed due to Trigger generator.

parent be926f45
......@@ -793,7 +793,6 @@ begin
tseg2_dbt_width => 5,
tq_dbt_width => 8,
sjw_dbt_width => 5,
ipt_length => 4,
sync_trigger_count => 2,
sample_trigger_count => 3
......
......@@ -712,7 +712,6 @@ package can_components is
tseg2_dbt_width : natural := 5;
tq_dbt_width : natural := 8;
sjw_dbt_width : natural := 5;
ipt_length : natural := 3;
sync_trigger_count : natural range 2 to 8 := 2;
sample_trigger_count : natural range 2 to 8 := 3
);
......@@ -791,7 +790,6 @@ package can_components is
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal resync_edge_valid : in std_logic;
signal ipt_ok : in std_logic;
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
signal tseg_1 : in std_logic_vector(tseg1_width - 1 downto 0);
......@@ -834,7 +832,6 @@ package can_components is
signal h_sync_edge_valid : in std_logic;
signal exit_segm_req_nbt : in std_logic;
signal exit_segm_req_dbt : in std_logic;
signal ipt_ok : in std_logic;
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
signal tq_edge_nbt : in std_logic;
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Information processing Time checker.
--
-- Checks length of Information processing time after Sample point between
-- PH1 and PH2. Functions like a half-handshake. When 'ipt_req' comes,
-- internal shift register is preloaded. This shift register shifts each
-- clock cycle and after input value was shifted till the very end, 'ipt_gnt'
-- is set high and remains high till the next 'ipt_req'.
--------------------------------------------------------------------------------
-- Revision History:
-- 03.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity ipt_checker is
generic (
-- Reset polarity
reset_polarity : std_logic := '0';
-- Length of Information processing time in clock cycles.
ipt_length : natural range 2 to 8 := 4
);
port(
-----------------------------------------------------------------------
-- Clock and reset
-----------------------------------------------------------------------
signal clk_sys : in std_logic;
signal res_n : in std_logic;
-----------------------------------------------------------------------
-- Control interface (Handshake-like)
-----------------------------------------------------------------------
signal is_tseg2 : in std_logic;
signal ipt_gnt : out std_logic
);
end entity;
architecture rtl of ipt_checker is
-- Internal Shift register
signal ipt_sr : std_logic_vector(ipt_length - 2 downto 0);
signal ipt_sr_nxt : std_logic_vector(ipt_length - 2 downto 0);
-- Clock enable for internal shift register.
signal ipt_sr_ce : std_logic;
-- IPT shift register is empty
signal ipt_empty : std_logic;
-- IPT request (in beginning of TSEG2)
signal ipt_req : std_logic;
-- TSEG2 register
signal is_tseg2_r : std_logic;
---------------------------------------------------------------------------
-- IPT constants
---------------------------------------------------------------------------
constant IPT_ZEROES : std_logic_vector(ipt_length - 2 downto 0) :=
(OTHERS => '0');
constant IPT_ONES : std_logic_vector(ipt_length - 2 downto 0) :=
(OTHERS => '1');
begin
---------------------------------------------------------------------------
-- TSEG2 registering, request formed in the beginning of TSEG2
---------------------------------------------------------------------------
tseg2_reg_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
is_tseg2_r <= '0';
elsif (rising_edge(clk_sys)) then
is_tseg2_r <= is_tseg2;
end if;
end process;
ipt_req <= '1' when (is_tseg2 = '1' and is_tseg2_r = '0') else
'0';
---------------------------------------------------------------------------
-- Shift register clock enable. Tick when:
-- 1. There is a request to measure IPT till grant (shift reg preload)
-- 2. Shift register is not empty, shifting is in progress.
---------------------------------------------------------------------------
ipt_sr_ce <= '1' when (ipt_req = '1') else
'1' when (ipt_empty = '0') else
'0';
-- Is shift register empty??
ipt_empty <= '1' when (ipt_sr = IPT_ZEROES) else
'0';
---------------------------------------------------------------------------
-- IPT Shift register. Next value:
-- 1. Preload upon request
-- 2. Shift to the right
---------------------------------------------------------------------------
ipt_sr_nxt <= IPT_ONES when (ipt_req = '1') else
'0' & ipt_sr(ipt_length - 2 downto 1);
---------------------------------------------------------------------------
-- IPT Shift register. Register assignment
---------------------------------------------------------------------------
ipt_sr_proc : process(res_n, clk_sys)
begin
if (res_n = reset_polarity) then
ipt_sr <= IPT_ZEROES;
elsif (rising_edge(clk_sys)) then
if (ipt_sr_ce = '1') then
ipt_sr <= ipt_sr_nxt;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Grant computation. We grant only if the shift register has shifted
-- till the very end!
---------------------------------------------------------------------------
ipt_gnt <= '1' when (ipt_empty = '1' and ipt_req = '0') else
'0';
---------------------------------------------------------------------------
-- Check that no next IPT request will come till grant to the first
-- request has been given. This should not occur since there should not
-- be sample points so close to each other.
---------------------------------------------------------------------------
-- psl ipt_half_handshake_asrt :
-- assert (not (ipt_empty = '0' and ipt_req = '1'));
end architecture rtl;
\ No newline at end of file
......@@ -97,9 +97,6 @@ entity prescaler is
tq_dbt_width : natural := 8;
sjw_dbt_width : natural := 5;
-- Length of information processing time (in clock cycles)
ipt_length : natural := 3;
-- Number of signals in Sync trigger
sync_trigger_count : natural range 2 to 8 := 2;
......@@ -205,9 +202,6 @@ architecture rtl of prescaler is
signal resync_edge_valid : std_logic;
signal h_sync_edge_valid : std_logic;
-- Information processing Time has elapsed, TSEG2 may end
signal ipt_ok : std_logic;
-- Size of internal Bit time counters.
constant bt_width_nbt : natural :=
max(tseg1_nbt_width, tseg2_nbt_width) + 1;
......@@ -302,21 +296,7 @@ begin
h_sync_edge_valid => h_sync_edge_valid
);
---------------------------------------------------------------------------
-- Information processing time checker
---------------------------------------------------------------------------
ipt_checker_comp : ipt_checker
generic map(
reset_polarity => reset_polarity,
ipt_length => ipt_length
)
port map(
clk_sys => clk_sys,
res_n => res_n,
is_tseg2 => is_tseg2,
ipt_gnt => ipt_ok
);
---------------------------------------------------------------------------
-- Re-synchronisation (Nominal Bit Time)
---------------------------------------------------------------------------
......@@ -332,7 +312,6 @@ begin
clk_sys => clk_sys,
res_n => res_n,
resync_edge_valid => resync_edge_valid,
ipt_ok => ipt_ok,
is_tseg1 => is_tseg1,
is_tseg2 => is_tseg2,
tseg_1 => tseg1_nbt,
......@@ -382,7 +361,6 @@ begin
clk_sys => clk_sys,
res_n => res_n,
resync_edge_valid => resync_edge_valid,
ipt_ok => ipt_ok,
is_tseg1 => is_tseg1,
is_tseg2 => is_tseg2,
tseg_1 => tseg1_dbt,
......@@ -430,7 +408,6 @@ begin
h_sync_edge_valid => h_sync_edge_valid,
exit_segm_req_nbt => exit_segm_req_nbt,
exit_segm_req_dbt => exit_segm_req_dbt,
ipt_ok => ipt_ok,
is_tseg1 => is_tseg1,
is_tseg2 => is_tseg2,
tq_edge_nbt => tq_edge_nbt,
......
......@@ -195,10 +195,7 @@ entity resynchronisation is
-----------------------------------------------------------------------
-- There is a valid re-synchronisation edge
signal resync_edge_valid : in std_logic;
-- Information processing time OK, PH2 may end
signal ipt_ok : in std_logic;
-----------------------------------------------------------------------
-- Bit Time FSM interface
-----------------------------------------------------------------------
......@@ -432,8 +429,7 @@ begin
---------------------------------------------------------------------------
-- Capture request to end of segment. Re-synchronisation is not Time Quanta
-- aligned, so we must capture the flag.
-- 1. Immediate exit of PH2, we still need to capture in case that this
-- resynchronisation is delayed till IPT_OK.
-- 1. Immediate exit of PH2.
-- 2. PH2, regular segment exit.
-- 3. PROP or PH1 regular segment exit.
---------------------------------------------------------------------------
......
......@@ -96,9 +96,6 @@ entity segment_end_detector is
signal exit_segm_req_nbt : in std_logic;
signal exit_segm_req_dbt : in std_logic;
-- Information processing time has elapsed after Sample point
signal ipt_ok : in std_logic;
-- Bit time segments indication
signal is_tseg1 : in std_logic;
signal is_tseg2 : in std_logic;
......@@ -260,15 +257,14 @@ begin
'0';
---------------------------------------------------------------------------
-- Time segment end requests. Note that for TSEG2 we must take IPT into
-- account!
-- Time segment end requests.
---------------------------------------------------------------------------
tseg1_end_req_valid <=
'1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else
'0';
tseg2_end_req_valid <=
'1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1' and ipt_ok = '1')
'1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1')
else
'0';
......
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