Commit e00cf5c4 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Remove hard-coded 0x3 address. Reduce adddress to 16 bits.

ID bits were moved to bits 15:12 to keep the address with only
as long as necesssary.
parent 1ca73e22
......@@ -81,7 +81,7 @@ entity apb_ifc is
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(23 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
reg_be_o : out std_logic_vector(3 downto 0);
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
......@@ -119,9 +119,6 @@ begin
reg_data_in_o <= s_apb_pwdata;
s_apb_prdata <= reg_data_out_i;
reg_addr_o(COMP_TYPE_ADRESS_HIGHER downto COMP_TYPE_ADRESS_LOWER) <=
CAN_COMPONENT_TYPE;
reg_addr_o(ID_ADRESS_HIGHER downto ID_ADRESS_LOWER) <=
std_logic_vector(to_unsigned(ID, 4));
......
......@@ -104,7 +104,7 @@ architecture rtl of CTU_CAN_FD_v1_0 is
signal reg_data_in : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal reg_addr : std_logic_vector(23 downto 0);
signal reg_addr : std_logic_vector(15 downto 0);
signal reg_be : std_logic_vector(3 downto 0);
signal reg_rden : std_logic;
signal reg_wren : std_logic;
......
......@@ -129,7 +129,7 @@ entity can_top_level is
---------------------
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic; --Chip select
signal srd : in std_logic; --Serial read
signal swr : in std_logic; --Serial write
......@@ -512,7 +512,6 @@ begin
memory_registers_comp : memory_registers
generic map(
compType => CAN_COMPONENT_TYPE,
use_logger => use_logger,
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
......
......@@ -86,7 +86,7 @@ package can_components is
signal res_n : in std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic;
signal srd : in std_logic;
signal swr : in std_logic;
......@@ -116,7 +116,6 @@ package can_components is
----------------------------------------------------------------------------
component memory_registers is
generic(
constant compType : std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
constant use_logger : boolean := true;
constant sup_filtA : boolean := true;
constant sup_filtB : boolean := true;
......@@ -135,7 +134,7 @@ package can_components is
signal res_out : out std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic;
signal srd : in std_logic;
signal swr : in std_logic;
......@@ -1164,7 +1163,7 @@ package can_components is
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(23 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
reg_be_o : out std_logic_vector(3 downto 0);
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
......
......@@ -154,30 +154,13 @@ package can_constants is
----------------------------------------------------------------------------
-- Memory Access
----------------------------------------------------------------------------
-- General Purpose register
constant GPR_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"1";
-- OutPut Multiplexor component type
constant OUTMUX_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"2";
-- FlexRay Node
constant FLEXRAY_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"3";
-- CAN Node
constant CAN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"4";
-- LIN Node
constant LIN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"5";
constant ACT_CSC : std_logic := '1';
constant ACT_SRD : std_logic := '1';
constant ACT_SWR : std_logic := '1';
-- Address ranges for component type and identifier
constant COMP_TYPE_ADRESS_HIGHER : natural := 23;
constant COMP_TYPE_ADRESS_LOWER : natural := 20;
constant ID_ADRESS_HIGHER : natural := 19;
constant ID_ADRESS_LOWER : natural := 16;
-- Address ranges for identifier
constant ID_ADRESS_HIGHER : natural := 15;
constant ID_ADRESS_LOWER : natural := 12;
constant CAN_DEVICE_ID : std_logic_vector(31 downto 0) := x"0000CAFD";
......
......@@ -148,8 +148,6 @@ use work.can_registers_pkg.all;
entity memory_registers is
generic(
constant compType :std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
-- Whenever event logger is present
constant use_logger :boolean := true;
......@@ -190,7 +188,7 @@ entity memory_registers is
------------------------------------------------------------------------
signal data_in :in std_logic_vector(31 downto 0);
signal data_out :out std_logic_vector(31 downto 0);
signal adress :in std_logic_vector(23 downto 0);
signal adress :in std_logic_vector(15 downto 0);
signal scs :in std_logic;
signal srd :in std_logic;
signal swr :in std_logic;
......@@ -392,8 +390,6 @@ begin
end generate txtb_cs_gen;
can_core_cs <= '1' when (scs = ACT_CSC) and
(adress(COMP_TYPE_ADRESS_HIGHER downto
COMP_TYPE_ADRESS_LOWER) = compType) and
(adress(ID_ADRESS_HIGHER downto ID_ADRESS_LOWER) =
std_logic_vector(to_unsigned(ID, 4)))
else
......@@ -446,7 +442,7 @@ begin
control_registers_reg_map_comp : control_registers_reg_map
generic map(
DATA_WIDTH => 32,
ADDRESS_WIDTH => 24,
ADDRESS_WIDTH => 16,
REGISTERED_READ => true,
CLEAR_READ_DATA => true,
RESET_POLARITY => ACT_RESET,
......@@ -480,7 +476,7 @@ begin
event_logger_reg_map_comp : event_logger_reg_map
generic map(
DATA_WIDTH => 32,
ADDRESS_WIDTH => 24,
ADDRESS_WIDTH => 16,
CLEAR_READ_DATA => true,
REGISTERED_READ => true,
RESET_POLARITY => ACT_RESET
......
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