Commit be926f45 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Prescaler model clean-up.

parent 405113fb
......@@ -74,9 +74,6 @@ package models_pkg is
component prescaler_model is
generic(
reset_polarity : std_logic := '0';
ipt_length : natural := 3;
sync_trigger_count : natural range 2 to 8 := 2;
sample_trigger_count : natural range 2 to 8 := 3;
clock_period : time := 10 ns
);
port(
......@@ -85,15 +82,8 @@ package models_pkg is
signal sync_edge :in std_logic; --Edge for synchronisation
signal OP_State :in oper_mode_type; --Protocol control state
signal drv_bus :in std_logic_vector(1023 downto 0);
signal clk_tq_nbt :out std_logic;
signal clk_tq_dbt :out std_logic;
signal sample_nbt :out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sample_dbt :out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sync_nbt :out std_logic_vector(sync_trigger_count - 1 downto 0);
signal sync_dbt :out std_logic_vector(sync_trigger_count - 1 downto 0);
signal bt_FSM_out :out bit_time_type;
signal data_tx :in std_logic;
signal hard_sync_edge_valid :out std_logic;
signal sp_control :in std_logic_vector(1 downto 0);
signal sync_control :in std_logic_vector(1 downto 0)
);
......
......@@ -66,6 +66,8 @@
-- These flags are also set for TSEG1 process when edge occured in TSEG2, so
-- that resync edge would not be considered more times between two sample
-- points!
--
-- TODO: Model does not implement trigger sequences so far!
--
--------------------------------------------------------------------------------
-- Revision History:
......@@ -95,71 +97,36 @@ entity prescaler_model is
-- Reset polarity
reset_polarity : std_logic := '0';
-- Length of information processing time (in clock cycles)
ipt_length : natural := 3;
-- Number of signals in Sync trigger
sync_trigger_count : natural range 2 to 8 := 2;
-- Number of signals in Sample trigger
sample_trigger_count : natural range 2 to 8 := 3;
-- Clock period
clock_period : time := 10 ns
);
port(
---------------------------------------------------------------------------
-- Clock and async reset
---------------------------------------------------------------------------
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async reset
---------------------------------------------------------------------------
-- Bus synch Interface
---------------------------------------------------------------------------
signal sync_edge :in std_logic; --Edge for synchronisation
signal OP_State :in oper_mode_type; --Protocol control state
--Driving Bus
signal drv_bus :in std_logic_vector(1023 downto 0);
---------------------------------------------------------------------------
-- Generated clock
---------------------------------------------------------------------------
--Time quantum clock - Nominal bit time
signal clk_tq_nbt :out std_logic;
--Time quantum - Data bit time
signal clk_tq_dbt :out std_logic;
---------------------------------------------------------------------------
-- Sample signals and delayed signals
---------------------------------------------------------------------------
signal sample_nbt :out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sample_dbt :out std_logic_vector(sample_trigger_count - 1 downto 0);
---------------------------------------------------------------------------
-- Sync Signals
---------------------------------------------------------------------------
signal sync_nbt :out std_logic_vector(sync_trigger_count - 1 downto 0);
signal sync_dbt :out std_logic_vector(sync_trigger_count - 1 downto 0);
signal bt_FSM_out :out bit_time_type;
-- What is actual node transmitting on the bus
signal data_tx :in std_logic;
-----------------------------------------------------------------------
-- Clock and async reset
-----------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-----------------------------------------------------------------------
-- Bus synch Interface
-----------------------------------------------------------------------
signal sync_edge :in std_logic;
signal OP_State :in oper_mode_type;
-- Driving Bus
signal drv_bus :in std_logic_vector(1023 downto 0);
-- Bit time FSM output
signal bt_FSM_out :out bit_time_type;
-- Validated hard synchronisation edge to start Protocol control FSM
-- Note: Sync edge from busSync.vhd cant be used! If it comes during sample
-- nbt, sequence it causes errors! It needs to be strictly before or
-- strictly after this sequence!!!
signal hard_sync_edge_valid :out std_logic;
-- What is actual node transmitting on the bus
signal data_tx :in std_logic;
---------------------------------------------------------------------------
-- Bit time and Synchronisation config
---------------------------------------------------------------------------
signal sp_control :in std_logic_vector(1 downto 0);
signal sync_control :in std_logic_vector(1 downto 0)
-----------------------------------------------------------------------
-- Bit time and Synchronisation config
-----------------------------------------------------------------------
signal sp_control :in std_logic_vector(1 downto 0);
signal sync_control :in std_logic_vector(1 downto 0)
);
end entity;
......@@ -515,6 +482,7 @@ begin
---------------------------------------------------------------------------
-- Bit time process
-- Counts TSEG1 and starts TSEG2 processes for NBT and for DBT.
---------------------------------------------------------------------------
bt_proc : process
variable exp_dur : integer := 0;
......
......@@ -41,8 +41,7 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Unit test for the prescaler circuit. At the time of implementation
-- "prescaler_v3.vhd" was used!
-- Unit test for the prescaler circuit.
--------------------------------------------------------------------------------
-- Revision History:
-- 7.6.2016 Created file
......@@ -51,6 +50,7 @@
-- 29.3.2018 Added check for the bit-rate switching to verify the compen-
-- sation mechanism, and provide stable reference in case of
-- reimplementation.
-- 12.3.2019 Replaced direct checks by a model of prescaler.
--------------------------------------------------------------------------------
context work.ctu_can_synth_context;
......@@ -158,6 +158,8 @@ architecture presc_unit_test of CAN_test is
-- Random counter for synchronisation edge generation
signal rand_ctr_sync_edge : natural range 0 to RAND_POOL_SIZE := 0;
-- No positive re-synchronisation
signal no_pos_resync : std_logic;
---------------------------------------------------------------------------
-- Model outputs
......@@ -307,19 +309,16 @@ begin
clk_sys => clk_sys,
res_n => res_n,
sync_edge => sync_edge,
OP_State => OP_State,
drv_bus => drv_bus ,
clk_tq_nbt => clk_tq_nbt,
clk_tq_dbt => clk_tq_dbt,
sample_nbt => sample_nbt_i,
sample_dbt => sample_dbt_i,
sync_nbt => sync_nbt_i,
sync_dbt => sync_dbt_i,
data_tx => data_tx,
bt_FSM_out => bt_FSM_out,
hard_sync_edge_valid => hard_sync_edge_valid,
sp_control => sp_control,
sync_control => sync_control
sync_control => sync_control,
no_pos_resync => no_pos_resync
);
-- Connect new vector signals to old signals for backwards compatibility
......@@ -376,6 +375,9 @@ begin
trig_signals.sync_nbt_del_1 <= sync_nbt_del_1;
trig_signals.sync_dbt_del_1 <= sync_dbt_del_1;
no_pos_resync <= '1' when (OP_State = transciever and data_tx = DOMINANT)
else
'0';
----------------------------------------------------------------------------
-- Clock generation
......@@ -558,8 +560,6 @@ begin
wait for 50 ns;
error("Bit time FSM state mismatch");
end if;
-- TODO: Implement checks with SYNC and SAMPLE signals!
end if;
end process;
......@@ -570,29 +570,19 @@ begin
---------------------------------------------------------------------------
prescaler_model_comp : prescaler_model
generic map(
reset_polarity => '0',
ipt_length => 3,
sync_trigger_count => 2,
sample_trigger_count => 3,
clock_period => 10 ns
reset_polarity => '0',
clock_period => 10 ns
)
port map(
clk_sys => clk_sys,
res_n => res_n,
sync_edge => sync_edge,
OP_State => OP_State,
drv_bus => drv_bus,
clk_tq_nbt => clk_tq_nbt_mod,
clk_tq_dbt => clk_tq_dbt_mod,
sample_nbt => sample_nbt_mod,
sample_dbt => sample_dbt_mod,
sync_nbt => sync_nbt_mod,
sync_dbt => sync_dbt_mod,
bt_FSM_out => bt_FSM_mod,
data_tx => data_tx,
hard_sync_edge_valid => hard_sync_edge_valid_mod,
sp_control => sp_control,
sync_control => sync_control
clk_sys => clk_sys,
res_n => res_n,
sync_edge => sync_edge,
OP_State => OP_State,
drv_bus => drv_bus,
bt_FSM_out => bt_FSM_mod,
data_tx => data_tx,
sp_control => sp_control,
sync_control => sync_control
);
......
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